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公开(公告)号：KR1020060018323A
公开(公告)日：2006-03-02
申请号：KR1020040066648
申请日：2004-08-24
Applicant: 삼성전자주식회사
IPC: H01L21/304
CPC classification number: C23C16/4405
Abstract: 처리 챔버에 존재하는 불순물을 제거하기 위한 챔버의 클리닝 방법으로, 공정챔버 내에서 산소가스/수소가스가 1: 1 ~ 40 유량비로 혼합된 혼합가스를 플라즈마 상태로 형성한 후 이를 적용하여 상기 공정 챔버 내에 흡착된 산화 텅스텐 오염물을 텅스텐으로 환원시켜 제거하는데 그 특징이 있다. 상술한 클리닝 방법을 기존의 클리닝 공정보다 빠르게 오염물을 제거할 수 있을 뿐만 아니라 파티클의 생성을 억제할 수 있다.
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公开(公告)号：KR1020050115822A
公开(公告)日：2005-12-08
申请号：KR1020050004616
申请日：2005-01-18
Applicant: 삼성전자주식회사
IPC: H01L21/336
Abstract: 트랜지스터의 매몰 게이트 전극 및 그 형성방법을 제공한다. 이 게이트 전극은 기판에 형성된 트렌치와, 상기 트렌치의 내벽을 콘포말하게 덮으며 중앙에 갭 영역을 가지는 실리콘 패턴을 포함한다. 텅스텐 패턴이 상기 실리콘 패턴의 갭 영역에 채워지고, 상기 실리콘 패턴 및 상기 텅스텐 패턴 사이에 접착층 패턴이 개재되어 있다. 상기 실리콘 패턴 및 상기 텅스텐 패턴의 상부를 캐핑층이 덮는다. 따라서, 상기 실리콘 패턴 및 상기 텅스텐 패턴 계면의 단부는 상기 캐핑층에 의해 덮여질 수 있다. 상기 실리콘 패턴은 기판면으로 부터 수직으로 신장된 측벽을 가질 수 있다. 상기 실리콘 패턴의 측벽은 상기 캐핑층의 측벽에 정렬된다. 상기 실리콘 패턴의 신장된 측벽에 게이트 폴리 산화막이 형성될 수 있다.
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公开(公告)号：KR1020050074777A
公开(公告)日：2005-07-19
申请号：KR1020040002666
申请日：2004-01-14
Applicant: 삼성전자주식회사
IPC: H01L21/28
CPC classification number: H01L21/7684 , H01L21/28556 , H01L21/76846 , H01L21/76856
Abstract: iPVD-Ti막 및 MOCVD-TiN막으로 이루어지는 배리어막에서 MOCVD-TiN막을 형성하기 전에 iPVD-Ti막 표면을 플라즈마 분위기하에서 질화처리하거나 iPVD-Ti막 위에 iPVD 방법으로 TiN막을 형성하여 반응 방지층을 형성하는 반도체 소자의 금속 배선 형성 방법에 관하여 개시한다. 본 발명에서는 반도체 기판상에 리세스 영역의 내벽을 구성하는 측벽과 상면을 가지는 절연막 패턴을 형성한다. 리세스 영역의 내벽 및 절연막 패턴의 상면에 iPVD 방법으로 Ti막을 형성한다. Ti막 중 절연막 패턴의 상면을 덮는 부분 위에 Ti막을 보호하기 위한 반응 방지층을 형성한다. 리세스 영역의 내부 및 절연막 패턴의 상면 위에 반응 방지층을 덮는 TiN막을 MOCVD 방법에 의하여 형성한다. TiN막 위에 리세스 영역 내부를 채우는 도전성 플러그를 형성한다.
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公开(公告)号：KR100447284B1
公开(公告)日：2004-09-07
申请号：KR1020020042598
申请日：2002-07-19
Applicant: 삼성전자주식회사
IPC: H01L21/304
CPC classification number: C23C16/4405
Abstract: After a processing chamber is used to deposit a refractory metal film on a substrate, the chamber is plasma-treated with a gas including either nitrogen and/or hydrogen and in-situ cleaned. By plasma-treating the chamber with a gas including nitrogen, the refractory metal film that forms on interior surfaces of the chamber during substrate processing is nitrided. The nitrided refractory metal film can be removed from the chamber during the in-situ cleaning. By plasma-treating the chamber with a gas including hydrogen, reaction by-products generated in the chamber is diluted removed. The chamber may be plasma-treated in a gas ambient including both nitrogen and hydrogen. Also, the plasma treatment may be performed before and after the in-situ cleaning.
Abstract translation: 在处理室用于在基底上沉积难熔金属膜之后，用包含氮气和/或氢气的气体对腔室进行等离子体处理并原位清洁。 通过用包含氮气的气体对腔室进行等离子体处理，在基板处理期间在腔室的内表面上形成的难熔金属膜被氮化。 氮化的难熔金属薄膜可以在现场清理过程中从腔室中取出。 通过用包含氢气的气体对腔室进行等离子体处理，将在腔室中产生的反应副产物稀释除去。 腔室可以在包括氮气和氢气的气体环境中进行等离子体处理。 而且，等离子体处理可以在原位清洁之前和之后进行。
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公开(公告)号：KR1020040017038A
公开(公告)日：2004-02-26
申请号：KR1020020049131
申请日：2002-08-20
Applicant: 삼성전자주식회사
IPC: H01L21/28
CPC classification number: H01L21/76843 , H01L21/28518 , H01L21/76802 , H01L21/76831 , H01L21/76855
Abstract: PURPOSE: A method for fabricating a contact structure of a semiconductor device is provided to prevent conductive layers adjacent to a cobalt silicide layer formed for an ohmic contact from being short-circuited by forming a spacer on the inner sidewall of a contact hole passing through an interlayer dielectric. CONSTITUTION: The interlayer dielectric(20) is formed on a substrate(2) with a conductive region. The contact hole is formed which passes through the interlayer dielectric and exposes the conductive region. The spacer(24) is formed on the inner sidewall of the contact hole. The cobalt silicide layer(30) is formed on the bottom surface of the contact hole having the spacer on its inner sidewall. A conductive layer(38) for filling the contact hole is formed on the cobalt silicide layer.
Abstract translation: 目的：提供一种用于制造半导体器件的接触结构的方法，以通过在穿过一个接触孔的接触孔的内侧壁上形成间隔物来防止与为欧姆接触形成的钴硅化物层相邻的导电层短路 层间电介质。 构成：层间电介质（20）形成在具有导电区域的基板（2）上。 形成穿过层间电介质并暴露导电区域的接触孔。 间隔件（24）形成在接触孔的内侧壁上。 钴硅化物层（30）形成在其内壁上具有间隔物的接触孔的底表面上。 在硅化钴层上形成用于填充接触孔的导电层（38）。
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Patent Agency Ranking
公开(公告)号：KR1020040010872A
公开(公告)日：2004-02-05
申请号：KR1020020043899
申请日：2002-07-25
Applicant: 삼성전자주식회사
IPC: H01L21/28
Abstract: PURPOSE: A semiconductor device having a crackless contact plug and a manufacturing method thereof are provided to prevent cracks from occurring inside an interlayer dielectric by forming a plug of a low internal stress. CONSTITUTION: A line structure of a semiconductor device is provided with a semiconductor substrate(100) and an interlayer dielectric(110) formed at the upper portion of the semiconductor substrate. At this time, the interlayer dielectric includes a contact hole(H). The line structure further includes a barrier metal coated at the inner surface of the contact hole and a contact plug(145) filled into the contact hole. The barrier metal is made of a Ti layer(120) and a TiN layer(130). The contact plug contains Ti, Si, and N. Preferably, the contact plug includes a Ti1-xSixN layer.
Abstract translation: 目的：提供一种具有无缝接触塞及其制造方法的半导体器件，以通过形成内应力低的插塞来防止层间电介质内的裂纹发生。 构成：半导体器件的线结构设置有形成在半导体衬底的上部的半导体衬底（100）和层间电介质（110）。 此时，层间电介质包括接触孔（H）。 线结构还包括涂覆在接触孔的内表面处的阻挡金属和填充到接触孔中的接触插塞（145）。 阻挡金属由Ti层（120）和TiN层（130）制成。 接触塞包含Ti，Si和N.优选地，接触塞包括Ti1-xSixN层。
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公开(公告)号：KR1020030064477A
公开(公告)日：2003-08-02
申请号：KR1020020004786
申请日：2002-01-28
Applicant: 삼성전자주식회사
IPC: H01L21/28
Abstract: PURPOSE: A method of fabricating a semiconductor device having a contact hole is provided to prevent junction spiking by forming irregular sidewall metal layers at the sidewalls of a contact hole. CONSTITUTION: A metal layer is formed on a semiconductor substrate having a contact hole(106a). The metal layer comprises a bottom and a sidewall metal layer(107a,107b). The bottom metal layer is formed on the surface of an impurity diffusion layer exposed at the contact hole. The sidewall metal layer is formed on the upper sidewall of the contact hole on a protrusion portion(120) and the upper portion of an interlayer dielectric(105).
Abstract translation: 目的：提供一种制造具有接触孔的半导体器件的方法，以通过在接触孔的侧壁处形成不规则的侧壁金属层来防止接合尖峰。 构成：在具有接触孔（106a）的半导体衬底上形成金属层。 金属层包括底部和侧壁金属层（107a，107b）。 底部金属层形成在暴露在接触孔处的杂质扩散层的表面上。 侧壁金属层形成在突出部分（120）和层间电介质（105）的上部的接触孔的上侧壁上。
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公开(公告)号：KR1020030064476A
公开(公告)日：2003-08-02
申请号：KR1020020004785
申请日：2002-01-28
Applicant: 삼성전자주식회사
IPC: H01L21/768
Abstract: PURPOSE: A method for fabricating a semiconductor device having a contact plug is provided to reduce the amount of chlorine by forming a void in the inside of a contact hole. CONSTITUTION: An interlayer dielectric(102) is formed on a semiconductor substrate(100). A contact hole(103) is formed by patterning the interlayer dielectric. A titanium layer is formed on the surface of the semiconductor substrate including the contact hole. A titanium nitride layer is formed on the titanium layer in order to form a void at the inside of the contact hole. A titanium nitride layer contact plug is formed by planarizing the contact plug layer and the titanium layer. A wire(107) is formed on an upper portion of the titanium nitride layer contact plug after the titanium nitride layer contact plug is formed.
Abstract translation: 目的：提供一种用于制造具有接触塞的半导体器件的方法，以通过在接触孔的内部形成空隙来减少氯的量。 构成：在半导体衬底（100）上形成层间电介质（102）。 通过图案化层间电介质形成接触孔（103）。 在包括接触孔的半导体衬底的表面上形成钛层。 在钛层上形成氮化钛层，以在接触孔的内部形成空隙。 通过使接触塞层和钛层平坦化形成氮化钛层接触塞。 在形成氮化钛层接触插塞之后，在氮化钛层接触插塞的上部形成导线（107）。
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公开(公告)号：KR100366639B1
公开(公告)日：2003-01-06
申请号：KR1020010015248
申请日：2001-03-23
Applicant: 삼성전자주식회사
Inventor： 박희숙
IPC: H01L21/28
CPC classification number: H01L27/10855 , H01L21/76802 , H01L21/76808 , H01L27/105 , H01L27/10894
Abstract: A method for forming a contact of a semiconductor device is disclosed. A first interlevel dielectric (ILD) layer is formed on a conductive region, e.g., an active region. The first ILD layer is etched to form a first contact hole therein to expose the conductive region. The first contact hole is filled with a porous layer having a high etch selectivity with respect to the first ILD layer to form a porous plug therein. Next, a second ILD layer is formed overlying the porous plug. The second ILD layer is etched to form a second contact hole therein to expose the porous plug. The porous plug in the first contact hole is removed. The first and second contact holes are filled with a conductive material to form a contact plug. During this contact formation process, the active region or the conductive region of the semiconductor substrate can be protected with the porous plug. Thus, the electrical characteristics degradation caused by dopant diffusion resulting from a thermal process during contact formation can be avoided.
Abstract translation: 公开了一种用于形成半导体器件的触点的方法。 第一层间电介质（ILD）层形成在导电区域，例如有源区域上。 蚀刻第一ILD层以在其中形成第一接触孔以暴露导电区域。 第一接触孔填充有相对于第一ILD层具有高蚀刻选择性的多孔层，以在其中形成多孔塞。 接下来，形成覆盖多孔插塞的第二ILD层。 蚀刻第二ILD层以在其中形成第二接触孔以暴露多孔塞。 第一接触孔中的多孔插塞被移除。 第一和第二接触孔填充有导电材料以形成接触插塞。 在该接触形成过程期间，半导体衬底的有源区或导电区可以用多孔插塞来保护。 因此，可以避免由接触形成过程中的热过程引起的掺杂剂扩散引起的电特性劣化。
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公开(公告)号：KR1020020075065A
公开(公告)日：2002-10-04
申请号：KR1020010015248
申请日：2001-03-23
Applicant: 삼성전자주식회사
Inventor： 박희숙
IPC: H01L21/28
CPC classification number: H01L27/10855 , H01L21/76802 , H01L21/76808 , H01L27/105 , H01L27/10894
Abstract: PURPOSE: A method for forming a contact is provided to prevent a doping element from being diffused from an active region of a semiconductor substrate, by protecting the active region in the course of forming a contact between the active region and an interconnection while using a porous oxide layer plug. CONSTITUTION: The first interlayer dielectric(210) which is dense and hard is formed on the semiconductor substrate(200). The first interlayer dielectric is etched to form the first contact hole opening the active region(202) of the semiconductor substrate. A porous oxide layer having high etch selectivity to the first interlayer dielectric is filled in the first contact hole to form the porous oxide layer plug. The second interlayer dielectric(220) which is dense and hard is formed on the semiconductor substrate having the porous oxide layer plug. The second interlayer dielectric is etched to form the second contact hole(222) exposing the upper portion of the buried first contact hole. The porous oxide layer filled in the first contact hole is eliminated. A conductive material is filled in the first and second contact holes to form a contact plug.
Abstract translation: 目的：提供一种用于形成接触的方法，以防止掺杂元件从半导体衬底的有源区扩散，通过在形成有源区和互连之间的接触的过程中保护有源区，同时使用多孔 氧化层塞。 构成：在半导体衬底（200）上形成致密且硬的第一层间电介质（210）。 蚀刻第一层间电介质以形成打开半导体衬底的有源区（202）的第一接触孔。 在第一接触孔中填充对第一层间电介质具有高蚀刻选择性的多孔氧化物层，以形成多孔氧化物层塞。 在具有多孔氧化物层塞的半导体基板上形成致密且硬的第二层间电介质（220）。 蚀刻第二层间电介质以形成暴露第一接触孔的上部的第二接触孔（222）。 消除了填充在第一接触孔中的多孔氧化物层。 导电材料填充在第一和第二接触孔中以形成接触塞。
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