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公开(公告)号：KR1020160013693A
公开(公告)日：2016-02-05
申请号：KR1020140095830
申请日：2014-07-28
Applicant: 삼성전자주식회사
IPC: H01L21/28
CPC classification number: H01L21/31111 , H01L21/02164 , H01L21/02167 , H01L21/0217 , H01L21/288 , H01L21/76816 , H01L21/76843 , H01L21/76844 , H01L21/76855 , H01L21/76879 , H01L21/76895 , H01L27/10855 , H01L29/4236 , H01L29/78
Abstract: 반도체소자및 그제조방법이제공된다. 상기반도체소자의제조방법은기판상에제1 및제2 소스드레인영역을포함하는트랜지스터및 상기트랜지스터의제1 소스드레인영역과연결되는비트라인을형성하고, 상기트랜지스터및 상기비트라인을덮는층간절연막을형성하고, 상기층간절연막을관통하여상기트랜지스터의상기제2 소스드레인영역을노출시키는제1 및제2 컨택홀을상기비트라인의양 측면에각각형성하고, 상기제1 및제2 컨택홀을메우고, 상기층간절연막상에형성되는희생막을형성하고, 상기희생막의적어도일부를제거하여상기제1 컨택홀을메우는희생막과상기제2 컨택홀을메우는희생막을서로분리하는제1 트렌치를형성하고, 상기제1 트렌치를메우는스페이서를형성하고, 상기희생막을제거하여상기제1 컨택홀상에서상기제1 컨택홀의일부및 상기제1 컨택홀의측면의상기층간절연막의일부와오버랩되는제2 트렌치를형성하고, 상기희생막을제거하여상기제2 컨택홀상에서상기제2 컨택홀의일부및 상기제2 컨택홀의측면의상기층간절연막의일부와오버랩되는제3 트렌치를형성하고, 상기제1 및제2 컨택홀을메우는컨택플러그를형성하고, 상기제2 및제3 트렌치를메우는메탈패턴을형성하는것을포함한다.
Abstract translation: 提供半导体部件及其制造方法。 半导体器件的制造方法包括：在衬底上形成包括第一和第二源极漏极的晶体管，以及与晶体管的第一源极漏极连接的位线; 形成覆盖晶体管和位线的层间绝缘膜; 形成穿透层间绝缘膜的第一和第二接触孔，以分别暴露位线两侧的晶体管的第二源极漏极区域; 填充第一和第二接触孔，并在层间绝缘膜上形成牺牲膜; 形成第一沟槽，通过去除所述牺牲膜的至少一部分，将填充所述第一接触孔的牺牲膜与填充所述第二接触孔的所述牺牲膜分离; 形成填充所述第一沟槽的间隔件; 在所述第一接触孔上形成与所述第一接触孔的一部分重叠的第二沟槽，并且通过去除所述牺牲膜，在所述第一接触孔的侧面上形成所述层间绝缘膜的一部分; 在所述第二接触孔上形成与所述第二接触孔的一部分重叠的第三沟槽，以及通过去除所述牺牲膜而与所述第二接触孔的侧面上的所述层间绝缘膜的一部分重叠; 形成填充所述第一和第二接触孔的接触塞; 以及形成填充所述第二和第三沟槽的金属图案。
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公开(公告)号：KR1020140030384A
公开(公告)日：2014-03-12
申请号：KR1020120093855
申请日：2012-08-27
Applicant: 삼성전자주식회사
IPC: H01L27/105
CPC classification number: H01L23/53266 , H01L23/528 , H01L23/53271 , H01L27/10817 , H01L27/10876 , H01L27/10885 , H01L27/10894 , H01L27/10897 , H01L27/228 , H01L28/91 , H01L29/0642 , H01L29/41766 , H01L29/42356 , H01L29/42372 , H01L29/66666 , H01L29/7827 , H01L2924/0002 , H01L2924/00
Abstract: The present invention provides a semiconductor device and a method for fabricating the same. The present invention provides a substrate including a cell array region and a peripheral circuit region. A cell gate structure embedded in the substrate of the cell array region is provided. A first impurity region and a second impurity region arranged at the both ends of the cell gate structure are provided. A conductive line connected to the first impurity region and arranged on the substrate is provided. A peripheral gate structure on the peripheral circuit region is provided. The conductive line and the peripheral gate structure include a first conductive pattern, a second conductive pattern, and an ohmic barrier pattern between the first conductive pattern and the second conductive pattern wherein the ohmic barrier pattern includes a metal-silicon nitride.
Abstract translation: 本发明提供一种半导体器件及其制造方法。 本发明提供一种包括单元阵列区域和外围电路区域的基板。 提供嵌入电池阵列区域的衬底中的电池栅极结构。 设置布置在单元栅极结构的两端的第一杂质区和第二杂质区。 提供连接到第一杂质区并布置在基板上的导线。 提供外围电路区域上的外围栅极结构。 导线和外围栅极结构包括在第一导电图案和第二导电图案之间的第一导电图案，第二导电图案和欧姆屏障图案，其中欧姆势垒图案包括金属 - 氮化硅。
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公开(公告)号：KR1020120003422A
公开(公告)日：2012-01-10
申请号：KR1020110140373
申请日：2011-12-22
Applicant: 삼성전자주식회사
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L29/42356 , H01L21/76831 , H01L29/66712
Abstract: PURPOSE: A buried gate electrode of a transistor and a forming method thereof are provided to prevent an interface oxidation of a silicon pattern by protecting the interface between a silicon pattern and an adhesive layer with a capping layer. CONSTITUTION: An adhesive layer is formed on a silicon layer with a gap area. A tungsten film filling the gap area is formed on the adhesive layer. The upper side of the silicon layer is exposed and a tungsten pattern(62p) filling the gap area and an adhesive pattern(60p) are formed. A capping layer(64) is formed on the front of a substrate(10) with the tungsten pattern and the adhesive pattern. A silicon pattern(58p) is formed by successively patterning the capping layer and the silicon layer.
Abstract translation: 目的：提供晶体管的掩埋栅电极及其形成方法，以通过用覆盖层保护硅图案和粘合剂层之间的界面来防止硅图案的界面氧化。 构成：在具有间隙面积的硅层上形成粘合剂层。 填充间隙区域的钨膜形成在粘合剂层上。 暴露硅层的上侧，形成填充间隙区域的钨图案（62p）和粘合剂图案（60p）。 在具有钨图案和粘合剂图案的衬底（10）的前部形成覆盖层（64）。 通过连续构图封盖层和硅层形成硅图案（58p）。
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公开(公告)号：KR1020090111932A
公开(公告)日：2009-10-28
申请号：KR1020080037556
申请日：2008-04-23
Applicant: 삼성전자주식회사
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L29/42324 , H01L21/28273 , H01L21/28282 , H01L27/10873 , H01L29/4941 , H01L29/517
Abstract: PURPOSE: A gate structures and a method of forming the same are provided to improve the thermal stability and the electrical characteristic by forming an Ohmic layer pattern with a high melting point metal like the titanium. CONSTITUTION: A gate structure comprises a gate insulating layer(110) on a substrate, a poly silicon layer on the gate insulating layer, an Ohmic layer on the poly silicon layer, a diffusion barrier on the Ohmic layer, an amorphous silicon on the diffusion barrier, and a metal layer on the amorphous silicon. The method of manufacturing a gate structure is as follows. The gate insulating layer is formed on the substrate. The poly silicon layer is formed on the gate insulating layer. The Ohmic layer is formed on the poly silicon layer. The diffusion barrier is formed on the Ohmic layer. The amorphous silicon layer is formed on the diffusion barrier. The metal layer is formed on the amorphous silicon layer.
Abstract translation: 目的：提供一种栅极结构及其形成方法，以通过形成具有像钛这样的高熔点金属的欧姆层图案来提高热稳定性和电特性。 构成：栅极结构包括在基板上的栅极绝缘层（110），栅极绝缘层上的多晶硅层，多晶硅层上的欧姆层，欧姆层上的扩散阻挡层，扩散层上的非晶硅 阻挡层和非晶硅上的金属层。 栅极结构的制造方法如下。 栅极绝缘层形成在基板上。 多晶硅层形成在栅极绝缘层上。 欧姆层形成在多晶硅层上。 扩散阻挡层在欧姆层上形成。 在扩散阻挡层上形成非晶硅层。 金属层形成在非晶硅层上。
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Patent Agency Ranking
公开(公告)号：KR100725369B1
公开(公告)日：2007-06-07
申请号：KR1020050134428
申请日：2005-12-29
Applicant: 삼성전자주식회사
IPC: H01L21/336
Abstract: 반도체 기판과 반도체 기판 상에 형성된 도우프된 도전막을 포함하는 반도체 소자가 제공된다. 확산 배리어막이 도우프된 도전막 상에 형성된다. 확산 배리어막은 비정질 반도체 물질을 포함한다. 오믹 콘택막이 확산 배리어막 상에 형성된다. 금속 배리어막이 오믹 콘택막 상에 형성된다. 금속막이 금속 배리어막 상에 형성된다.
비정질 실리콘막, 불순물이 도우프된 다결정 실리콘막, 반전 커패시턴스-
公开(公告)号：KR1020070034333A
公开(公告)日：2007-03-28
申请号：KR1020050088905
申请日：2005-09-23
Applicant: 삼성전자주식회사
IPC: H01L21/24 , H01L21/205
CPC classification number: H01L21/32053 , C23C16/42 , C23C16/4404 , H01L21/28061 , H01L29/517 , H01L29/6659
Abstract: A method of forming a tungsten silicide layer and a related method of fabricating a semiconductor element. The method of forming the tungsten silicide layer includes forming a pre-coating layer within a CVD process chamber by injecting a tungsten source gas (A) and a silicon source gas (B) at a flow ratio (A/B) of 1/50 or less, and thereafter loading a semiconductor substrate into the CVD process chamber in which the precoating layer is formed, and injecting additional tungsten source gas and silicon source gas to form the tungsten silicide layer on the semiconductor substrate.
Abstract translation: 一种形成硅化钨层的方法和制造半导体元件的相关方法。 形成硅化钨层的方法包括通过以1/50的流量比（A / B）注入钨源气体（A）和硅源气体（B），在CVD处理室内形成预涂层 然后将半导体衬底装载到其中形成预涂层的CVD工艺腔室中，并且注入额外的钨源气体和硅源气体以在半导体衬底上形成硅化钨层。
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公开(公告)号：KR100654358B1
公开(公告)日：2006-12-08
申请号：KR1020050073415
申请日：2005-08-10
Applicant: 삼성전자주식회사
IPC: H01L21/336
Abstract: A semiconductor integrated circuit device is provided to optimizing the capabilities of an N-type transistor and a P-type transistor by selectively forming an ohmic layer only in an N-type transistor whereas the ohmic layer is not formed in a P-type transistor. An N-type transistor region and a P-type transistor region are defined in a substrate(105). An N-type transistor(100) is formed in the N-type transistor region wherein a source/drain region(160), polysilicon and a metal layer(136) are stacked in the N-type transistor, including a gate electrode having an ohmic layer(132) and a barrier layer(134) between the polysilicon and the metal layer. A P-type transistor(101) is formed in the P-type transistor region wherein polysilicon and a metal layer are stacked in the P-type transistor, including a gate electrode having a barrier layer between the polysilicon and the metal layer. The polysilicon of the N-type transistor is N-type polysilicon(120N), and the polysilicon of the P-type transistor is P-type polysilicon(120P).
Abstract translation: 提供半导体集成电路器件以通过仅在N型晶体管中选择性地形成欧姆层而不在P型晶体管中形成欧姆层来优化N型晶体管和P型晶体管的能力。 N型晶体管区域和P型晶体管区域被限定在衬底（105）中。 在N型晶体管区域中形成N型晶体管（100），其中在N型晶体管中堆叠源极/漏极区域（160），多晶硅和金属层（136），所述N型晶体管包括具有 欧姆层（132）和位于多晶硅和金属层之间的阻挡层（134）。 在其中多晶硅和金属层堆叠在P型晶体管中的P型晶体管区域中形成P型晶体管（101），该P型晶体管包括在多晶硅和金属层之间具有阻挡层的栅电极。 N型晶体管的多晶硅为N型多晶硅（120N），P型晶体管的多晶硅为P型多晶硅（120P）。
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公开(公告)号：KR1020060025326A
公开(公告)日：2006-03-21
申请号：KR1020040074074
申请日：2004-09-16
Applicant: 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L27/11526 , H01L21/82345 , H01L27/105 , H01L27/1052 , H01L27/11546 , H01L21/28273
Abstract: A semiconductor device includes a first conductive layer on a semiconductor substrate, a dielectric layer including a high-k dielectric material on the first conductive layer, a second conductive layer including polysilicon doped with P-type impurities on the dielectric layer, and a third conductive layer including a metal on the second conductive layer. In some devices, a first gate structure is formed in a main cell region and includes a tunnel oxide layer, a floating gate, a first high-k dielectric layer, and a control gate. The control gate includes a layer of polysilicon doped with P-type impurities and a metal layer. A second gate structure is formed outside the main cell region and includes a tunnel oxide layer, a conductive layer, and a metal layer. A third gate structure is formed in a peripheral cell region and includes a tunnel oxide, a conductive layer, and a high-k dielectric layer having a width narrower than the conductive layer. Method embodiments are also disclosed.
Abstract translation: 一种半导体器件包括在半导体衬底上的第一导电层，在第一导电层上包括高k电介质材料的电介质层，包括在电介质层上掺杂有P型杂质的多晶硅的第二导电层，以及第三导电 在第二导电层上包括金属层。 在一些器件中，第一栅极结构形成在主单元区域中并且包括隧道氧化物层，浮置栅极，第一高k电介质层和控制栅极。 控制栅极包括掺杂有P型杂质的多晶硅层和金属层。 第二栅极结构形成在主单元区域外部并且包括隧道氧化物层，导电层和金属层。 第三栅极结构形成在周边单元区域中并且包括隧道氧化物，导电层和宽度比导电层窄的高k介电层。 还公开了方法实施例。
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公开(公告)号：KR100543458B1
公开(公告)日：2006-01-20
申请号：KR1020030035657
申请日：2003-06-03
Applicant: 삼성전자주식회사
IPC: H01L21/28
CPC classification number: H01L21/76843 , H01L21/28562 , H01L21/321 , H01L21/76862 , H01L21/76877 , H01L23/5226 , H01L23/53204 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L2924/0002 , H01L2924/00
Abstract: 반도체 장치의 도전성 구조체 형성 방법을 제공한다. 이 방법은 반도체기판 상에 하부 도전 패턴을 형성하고, 금속유기 전구체를 사용하여 베리어 금속막을 증착한 후, 증착된 베리어 금속막을 정화하는 단계를 포함한다. 베리어 금속막을 정화하는 단계는 TiCl
4 가스 및 아르곤 가스를 포함하는 공정 가스를 사용하여, 200 내지 500 ℃의 온도에서 실시하는 것이 바람직하다.
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