公开(公告)号：KR1020100099913A

公开(公告)日：2010-09-15

申请号：KR1020090018486

申请日：2009-03-04

Applicant: 삼성전자주식회사

Inventor： 김정인 ,  오재희 ,  김현호 ,  정지현

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L45/16 ,  H01L27/1021 ,  H01L27/24

Abstract: PURPOSE: A memory device forming method is provided to prevent the damage to a bottom electrode by forming an etching prevention layer of multi layer. CONSTITUTION: A bottom electrode(140) is formed on a substrate(100). A first etch stopping layer(150) and a second etch stopping layer(155) are formed on the bottom electrode. An insulating layer(160) is formed on the etch stopping layer. A recess area is formed to expose the bottom electrode by patterning the insulation layer and the etching prevention layer.

Abstract translation: 目的：提供一种存储器件形成方法，通过形成多层的防蚀层来防止对底部电极的损坏。 构成：在基板（100）上形成底部电极（140）。 第一蚀刻停止层（150）和第二蚀刻停止层（155）形成在底部电极上。 绝缘层（160）形成在蚀刻停止层上。 通过图案化绝缘层和防蚀层，形成凹部以暴露底部电极。

公开(公告)号：KR1020100081143A

公开(公告)日：2010-07-14

申请号：KR1020090000436

申请日：2009-01-05

Applicant: 삼성전자주식회사

Inventor： 박재현 ,  오재희 ,  은성호

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L45/124 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/141 ,  H01L45/1691 ,  H01L45/1683

Abstract: PURPOSE: A semiconductor phase change memory device is provided to make data storage structure, data contact structure, and a data line overlapped with each other by burying the data storage structure, the data contact structure, and the data line into the opening of the insulating layer. CONSTITUTION: A data Line(105) is formed on an active area(10). A data storage structure(55) locates under the data line. The data storage structure comprises a concave part along the data line. The data storage structure has the same center as the data line. The data contact structure includes a lower side filling the concave part of the data storage structure and also includes upper side surrounding the data line. A pad electrode(25) is arranged under data contact structure and data line.

Abstract translation: 目的：提供半导体相变存储器件，通过将数据存储结构，数据接触结构和数据线埋入绝缘的开口中，使数据存储结构，数据接触结构和数据线彼此重叠 层。 构成：数据线（105）形成在有源区（10）上。 数据存储结构（55）位于数据线之下。 数据存储结构包括沿数据线的凹部。 数据存储结构与数据线具有相同的中心。 数据接触结构包括填充数据存储结构的凹部的下侧，并且还包括围绕数据线的上侧。 焊盘电极（25）布置在数据接触结构和数据线之下。

公开(公告)号：KR1020100060891A

公开(公告)日：2010-06-07

申请号：KR1020080119681

申请日：2008-11-28

Applicant: 삼성전자주식회사

Inventor： 이길호 ,  오재희 ,  박재현

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L45/04 ,  H01L21/0226 ,  H01L21/265 ,  H01L21/31051 ,  H01L45/1233 ,  H01L45/141

Abstract: PURPOSE: A method for forming a resistance variable memory device is provided to reduce a manufacturing time of a variable resistance memory by forming an amorphous semiconductor layer and improving the speed of forming a diode. CONSTITUTION: In a method for forming a resistance variable memory device, an insulating layer having an opening on a substrate(100) is formed. An epilayer(130) is formed on the opening from the substrate by a first height(A1). An amorphous semiconductor layer(140) is formed on the epilayer. The amorphous semiconductor layer and the epilayer are recessed by a second height. The first height is higher than the second height.

Abstract translation: 目的：提供一种用于形成电阻可变存储器件的方法，通过形成非晶半导体层并提高形成二极管的速度来减少可变电阻存储器的制造时间。 构成：在形成电阻可变存储器件的方法中，形成在衬底（100）上具有开口的绝缘层。 在基板的开口上形成有第一高度（A1）的外延层（130）。 在外延层上形成非晶半导体层（140）。 非晶半导体层和外延层凹陷第二高度。 第一个高度高于第二个高度。

公开(公告)号：KR1020100048611A

公开(公告)日：2010-05-11

申请号：KR1020080107856

申请日：2008-10-31

Applicant: 삼성전자주식회사

Inventor： 이공수 ,  정지현 ,  오재희 ,  박재현 ,  김경석 ,  박상진 ,  이창훈

IPC: H01L21/28

CPC classification number: H01L27/1021 ,  H01L27/24 ,  H01L29/8613

Abstract: PURPOSE: A semiconductor device and a method for forming the same are provided to form a semiconductor pattern into a uniform mono-crystalline state by forming the semiconductor pattern with a selective epitaxial growth process. CONSTITUTION: An etching stop layer(120) and an interlayer insulation layer(130) are successively formed on a substrate(110). An opening and an under-cut region are formed. The opening successively passes through the etching stop layer and the interlayer insulation layer. A semiconductor pattern(140) is formed in the opening by performing a selective epitaxial growth process. A spacer is formed in the under-cut region. The spacer and the semiconductor pattern are simultaneously formed.

Abstract translation: 目的：提供一种半导体器件及其形成方法，以通过选择性外延生长工艺形成半导体图案，将半导体图案形成均匀的单晶态。 构成：在衬底（110）上依次形成蚀刻停止层（120）和层间绝缘层（130）。 形成开口和下切割区域。 开口依次通过蚀刻停止层和层间绝缘层。 通过执行选择性外延生长工艺在开口中形成半导体图案（140）。 在切割下区域形成间隔物。 同时形成间隔物和半导体图案。

公开(公告)号：KR1020090037664A

公开(公告)日：2009-04-16

申请号：KR1020070103114

申请日：2007-10-12

Applicant: 삼성전자주식회사

Inventor： 박재현 ,  오재희

IPC: H01L27/115 ,  H01L29/772 ,  H01L21/335

CPC classification number: H01L45/06 ,  H01L29/66409 ,  H01L29/772 ,  H01L45/1233 ,  H01L45/141

Abstract: A phase change random access memory device and a method for fabricating thereof are provided to increase current driving capacity of a switching device, so increasing integration. A pin body(108) having an upper side and side walls are protruded from a semiconductor substrate(102). A first and a second impurity region(116a,116b) are formed in the pin body while being separated each other. A gate electrode(112) covers the pin body formed at the first and a second impurity region. A data storage element is electrically connected with one of the first and second impurity region and it includes a phase change material film(130), a first electrode, and a second electrode.

Abstract translation: 提供了一种相变随机存取存储器件及其制造方法，以增加开关器件的电流驱动能力，从而增加集成度。 具有上侧和侧壁的销体（108）从半导体衬底（102）突出。 第一和第二杂质区域（116a，116b）形成在销体中，同时彼此分离。 栅电极（112）覆盖在第一和第二杂质区域形成的引脚体。 数据存储元件与第一和第二杂质区域之一电连接，并且其包括相变材料膜（130），第一电极和第二电极。

公开(公告)号：KR1020080099521A

公开(公告)日：2008-11-13

申请号：KR1020070045164

申请日：2007-05-09

Applicant: 삼성전자주식회사

Inventor： 김정인 ,  오재희 ,  공준혁 ,  박재현 ,  이광우

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/2409 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/141 ,  H01L45/1683 ,  G11C13/0004

Abstract: The damage of phase transition pattern can be prevented even if the alignment error caused by photolithography is generated while forming the bit line. Also, the high integration can be easily achieved. The manufacturing method of the memory device having the self-aligned electrode is provided. The interlayer insulating film(57) having the contact hole(57H) on the substrate(51) is formed. The phase transition pattern which partly fills the contact hole is formed. The bit line(93) which passes across the interlayer insulating film phase is formed, including the bit extension part(93E) self-aligned in the phase transition pattern. The bit extension part can be extended inside the contact hole on the phase transition pattern. The bit extension part is contacted with the phase transition pattern.

Abstract translation: 即使在形成位线时产生由光刻引起的对准误差，也可以防止相变图案的损坏。 此外，可以容易地实现高集成度。 提供具有自对准电极的存储器件的制造方法。 形成在基板（51）上具有接触孔（57H）的层间绝缘膜（57）。 形成部分填充接触孔的相变图案。 形成穿过层间绝缘膜相的位线（93），包括在相变图案中自对准的位延伸部分（93E）。 钻头延伸部分可以在相变图案的接触孔内延伸。 位延伸部分与相变图案接触。

公开(公告)号：KR100782496B1

公开(公告)日：2007-12-05

申请号：KR1020060110549

申请日：2006-11-09

Applicant: 삼성전자주식회사

Inventor： 은성호 ,  오재희 ,  박재현 ,  김정인 ,  고승필 ,  오용태

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/2463 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1675 ,  H01L21/76224 ,  H01L21/76897 ,  H01L45/04

Abstract: A method for manufacturing a semiconductor device having a self-aligned cell diode and a method for manufacturing a phase-change memory device using the same are provided to restrain increase of electrical resistance due to a mis-alignment of the word lines and cell diodes by using self-cell diodes being self-aligned with word lines. A conductive layer is formed on a semiconductor substrate(40). A dielectric(44) is formed on the conductive layer. The dielectric and the conductive layer are patterned in turn to form isolation trenches for exposing the substrate and word lines(WL) defined by the isolation trenches. An isolation layer(54) is formed to gap-fill the isolation trenches. Cell contact holes pass through to expose the word lines. The cell contact holes are defined by the adjacent isolation layer to be self-aligned with the word lines. Cell diodes gap-fill the cell contact holes. When the isolation trenches and the word lines are formed, a first hard mask layer is formed on the dielectric, the first hard mask layer is patterned to form a line-shaped first preliminary hard mask patterns(46'), and the dielectric is etched by using the first preliminary hard mask patterns as etch masks.

Abstract translation: 提供具有自对准单元二极管的半导体器件的制造方法和使用其的相变存储器件的制造方法，以抑制由于字线和单元二极管的错误对准引起的电阻的增加 使用自细胞二极管与字线自对准。 在半导体衬底（40）上形成导电层。 电介质（44）形成在导电层上。 电介质层和导电层依次进行图案化，形成用于暴露由隔离沟槽限定的衬底和字线（WL）的隔离沟槽。 形成隔离层（54）以间隔填充隔离沟槽。 细胞接触孔通过以暴露字线。 单元接触孔由相邻隔离层限定，以与字线自对准。 电池二极管间隙填充电池接触孔。 当形成隔离沟槽和字线时，在电介质上形成第一硬掩模层，将第一硬掩模层图案化以形成线状的第一初步硬掩模图案（46'），并且电介质被蚀刻 通过使用第一初步硬掩模图案作为蚀刻掩模。

公开(公告)号：KR100675279B1

公开(公告)日：2007-01-26

申请号：KR1020050032898

申请日：2005-04-20

Applicant: 삼성전자주식회사

Inventor： 박재현 ,  오재희 ,  이세호 ,  정원철

IPC: H01L27/115

CPC classification number: H01L45/144 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1666

Abstract: 셀 다이오드들을 채택하는 상변이 기억소자들을 제공한다. 상기 상변이 기억소자들은 제1 도전형의 반도체 기판 및 상기 반도체 기판 상부에 형성된 제1 층간절연막을 구비한다. 상기 제1 층간절연막을 관통하는 셀 다이오드 홀이 제공된다. 상기 셀 다이오드 홀의 하부 영역 내에 제1 및 제2 반도체 패턴들이 차례로 적층된다. 상기 제2 반도체 패턴 상에 셀 다이오드 전극이 제공된다. 상기 셀 다이오드 전극은 상기 제1 층간절연막의 상부면보다 낮은 표면을 갖는다. 상기 셀 다이오드 전극 상에 상기 셀 다이오드 홀을 채우는 국한된 상변이 물질 패턴(confined phase change material pattern)이 제공된다. 상기 국한된 상변이 물질 패턴 상에 상부전극이 배치된다. 상기 셀 다이오드 홀 내의 상기 국한된 상변이 물질 패턴은 상기 셀 다이오드 홀에 의해 상기 제1 및 제2 반도체 패턴들과 자기정렬된다. 상기 상변이 기억소자의 제조방법들 역시 제공된다.

Abstract translation: 提供采用单元二极管的顶级存储器元件。 上侧存储元件包括第一导电类型半导体衬底和形成在半导体衬底上的第一层间绝缘膜。 提供穿透第一层间绝缘膜的单元二极管孔。 第一和第二半导体图案顺序地堆叠在单元二极管孔的下部区域中。 在第二半导体图案上提供单元二极管电极。 单元二极管电极具有比第一层间绝缘膜的上表面低的表面。 在电池二极管电极上提供填充电池二极管孔的封闭相变材料图案。 上电极设置在局部上相材料图案上。 单元二极管孔中的局部相变材料图案通过单元二极管孔与第一和第二半导体图案自对准。 还提供了制造相变存储元件的方法。

公开(公告)号：KR100568849B1

公开(公告)日：2006-08-10

申请号：KR1019980057523

申请日：1998-12-23

Applicant: 삼성전자주식회사

Inventor： 오재희

IPC: H01L21/28

Abstract: 본 발명에 따른 반도체소자의 제조방법을 개시한다. 본 발명은 반도체기판에 소정 깊이를 갖는 트랜치를 형성한 다음, 트랜치의 내,외측에 CVD산화막을 형성하고 그 전면에 모노 실렌계의 폴리실리콘막을 형성한 후, 이를 열산화시켜 열산화막을 형성하여 트랜치를 채우게 된다. 따라서, 트랜치의 갭필용으로 CVD산화막을 증착할 때 트랜치내에 발생되는 보이드를 방지할 수 있어 트랜치의 갭필 특성을 향상시킬 수 있다.

公开(公告)号：KR1020030043408A

公开(公告)日：2003-06-02

申请号：KR1020010074571

申请日：2001-11-28

Applicant: 삼성전자주식회사

Inventor： 강동해 ,  오재희

IPC: H01L21/28

Abstract: PURPOSE: A semiconductor device with tungsten a plug cell pad is provided to minimize heat budget on the device during a deposition process and contact resistance between a contact plug and poly cell pad. CONSTITUTION: Gates(210) are formed on a semiconductor substrate(200) and then using them as a mask, active regions are formed. Spacers(220) are formed on the sidewall of gates(210) and an interlayer dielectrics(230) is formed on the resultant structure. The interlayer dielectrics is etched by using a cell pad photoresist, opening the gap between the spacers, as a mask to form an opening, through which ions are implanted on the exposed active region, so that contact ion implementation layer(240) is formed. A barrier metal layer(255) is formed on the resultant surface. A tungsten pad layer(265) is deposited around the temperature of 200 degree C. A planarization process such as CMP or etch-back one is done on the whole structure to form a tungsten cell pad.

Abstract translation: 目的：提供一种具有钨的塞子电池垫的半导体器件，以最小化沉积过程中器件的热量预算以及接触插塞和多晶硅电池焊盘之间的接触电阻。 构成：将栅极（210）形成在半导体衬底（200）上，然后使用它们作为掩模，形成有源区。 隔板（220）形成在栅极（210）的侧壁上，并且在所得结构上形成层间电介质（230）。 通过使用电池衬垫光致抗蚀剂来蚀刻层间电介质，打开间隔件之间的间隙作为掩模以形成开口，通过该开口将离子注入到暴露的有源区上，从而形成接触离子实施层（240）。 在所得表面上形成阻挡金属层（255）。 在200℃的温度附近沉积钨焊盘层（265）。在整个结构上进行诸如CMP或回蚀的平坦化工艺以形成钨电池焊盘。