公开(公告)号：KR1020120104041A

公开(公告)日：2012-09-20

申请号：KR1020110022109

申请日：2011-03-11

Applicant: 삼성전자주식회사

Inventor： 박상수 ,  오재희 ,  김정인

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L45/06 ,  H01L27/2409 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1608 ,  H01L21/28052 ,  H01L21/31051 ,  H01L45/143

Abstract: PURPOSE: A phase change memory device and a manufacturing method thereof are provided to reduce a voltage drop comparing a distance separated from a peripheral area with a word line, thereby minimizing cell distribution defects. CONSTITUTION: A substrate(40) includes a cell area(100) and a peripheral area(200). A word line(20) is extended to a first direction on the substrate of the cell area. A diode and a phase change resistor are formed on the word line. A transistor includes a gate stack formed on the substrate of the peripheral area. The word line includes a metal layer formed on the substrate in the same level with the gate stack. An element isolation layer formed in between the word line and the substrate is included in a phase change memory device.

Abstract translation: 目的：提供一种相变存储器件及其制造方法，以将与外围区域分离的距离与字线进行比较来降低电压降，从而最小化电池分布缺陷。 构成：衬底（40）包括电池区（100）和周边区（200）。 字线（20）在单元区域的基板上延伸到第一方向。 在字线上形成二极管和相变电阻。 晶体管包括形成在周边区域的基板上的栅极堆叠。 字线包括在与栅极叠层相同水平面的基板上形成的金属层。 形成在字线和基板之间的元件隔离层包括在相变存储器件中。

公开(公告)号：KR1020110113054A

公开(公告)日：2011-10-14

申请号：KR1020100032381

申请日：2010-04-08

Applicant: 삼성전자주식회사

Inventor： 정지현 ,  오재희 ,  주흥진 ,  은성호

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L45/06 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  G11C13/0004 ,  H01L45/143

Abstract: 가변 저항 메모리 소자 및 그 제조 방법을 제공한다. 기판 상에 오프닝을 포함하는 제 1 층간 절연막을 형성하고, 상기 오프닝의 측벽 상에 전극 보호 패턴을 형성하고, 상기 오프닝을 채우는 하부 전극을 형성하고, 상기 제 1 층간 절연막 상에, 상기 하부 전극의 상면을 노출하는 리세스 영역을 포함하는 제 2 층간 절연막을 형성한다. 상기 리세스 영역 내에 가변 저항 물질막을 형성한다. 상기 하부 전극의 상면은 상기 리세스 영역에 의하여 노출되는 상기 제 1 층간 절연막의 상면 보다 높다.

公开(公告)号：KR1020100090969A

公开(公告)日：2010-08-18

申请号：KR1020090010222

申请日：2009-02-09

Applicant: 삼성전자주식회사

Inventor： 은성호 ,  오재희

IPC: H01L21/8247 ,  H01L27/115 ,  H01L21/768

CPC classification number: H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1683

Abstract: PURPOSE: A method for manufacturing a phase change memory device is provided to increase a process margin by forming self-aligned upper electrode and bit lines through one photo process. CONSTITUTION: A phase change material film(190) is formed on a substrate. A damascene pattern is formed on the phase change material film. An insulating film is formed to cover the phase change material film on the substrate. The insulating film is patterned to form a contact hole for exposing the phase change material film. An upper electrode(230) and bit liens are formed in the damascene pattern.

Abstract translation: 目的：提供一种用于制造相变存储器件的方法，以通过一个照相工艺形成自对准的上电极和位线来增加工艺余量。 构成：在基板上形成相变材料膜（190）。 在相变材料膜上形成镶嵌图案。 形成绝缘膜以覆盖基板上的相变材料膜。 图案化绝缘膜以形成用于暴露相变材料膜的接触孔。 在镶嵌图案中形成上电极（230）和位留置体。

公开(公告)号：KR1020100027478A

公开(公告)日：2010-03-11

申请号：KR1020080086415

申请日：2008-09-02

Applicant: 삼성전자주식회사

Inventor： 박상수 ,  오재희 ,  임영수

IPC: H01L29/00

Abstract: PURPOSE: A method for forming a semiconductor device is provided to minimize by-products during an etching process by etching a capping layer and a variable resistance layer with a front-side dry-etching method. CONSTITUTION: An insulation layer(132) including a plurality of openings is formed on a substrate(110). A variable resistance layer(136) which fills the openings is formed on the upper side of the substrate. A capping layer(138) is formed on the variable resistance layer. The capping layer and the variable resistance layer are etched using a front-side dry-etching method. The front dry etching method is performed until the upper side of the insulation layer is exposed.

Abstract translation: 目的：提供一种用于形成半导体器件的方法，以通过用前侧干蚀刻方法蚀刻封盖层和可变电阻层来最小化蚀刻工艺期间的副产物。 构成：在基板（110）上形成包括多个开口的绝缘层（132）。 填充开口的可变电阻层（136）形成在基板的上侧。 在可变电阻层上形成覆盖层（138）。 使用前侧干蚀刻方法蚀刻覆盖层和可变电阻层。 进行前干式蚀刻方法直到绝缘层的上侧露出。

公开(公告)号：KR100883412B1

公开(公告)日：2009-02-11

申请号：KR1020070045164

申请日：2007-05-09

Applicant: 삼성전자주식회사

Inventor： 김정인 ,  오재희 ,  공준혁 ,  박재현 ,  이광우

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/2409 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/141 ,  H01L45/1683

Abstract: 자기 정렬된 전극을 갖는 상전이 메모리소자의 제조방법을 제공한다. 기판 상에 콘택 홀을 갖는 층간 절연막을 형성한다. 상기 콘택 홀을 부분적으로 채우는 상전이패턴을 형성한다. 상기 상전이패턴에 자기 정렬된 비트 연장부를 구비하며 상기 층간 절연막 상을 가로지르는 비트라인을 형성한다. 상기 비트 연장부는 상기 상전이패턴 상의 상기 콘택 홀 내부에 신장될 수 있다. 상기 비트 연장부는 상기 상전이패턴에 접촉된다.

公开(公告)号：KR1020080039701A

公开(公告)日：2008-05-07

申请号：KR1020060107337

申请日：2006-11-01

Applicant: 삼성전자주식회사

Inventor： 오용태 ,  오재희 ,  정창욱 ,  박재현 ,  김정인 ,  은성호 ,  고승필 ,  이광우

IPC: H01L27/115

CPC classification number: H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1666

Abstract: A phase change memory device and a method for forming the same are provided to widen the width of a cell hole in comparison with a minimum line width by performing sequentially a patterning process including an anisotropic etch process and an isotropic etch process. A dopant doping line(110) is formed on an upper surface of a semiconductor substrate(100). A mold insulating layer(120) is formed on the semiconductor substrate. A preliminary cell hole for exposing the dopant doping line is formed by patterning the mold insulating layer in an anisotropic etch method. A cell hole(125a) is formed by etching the mold insulating layer having the preliminary cell hole in an isotropic method. A diode(130) is formed within the cell hole. A heater electrode(140) is formed on the diode. A phase change pattern(145) is formed on the heater electrode.

Abstract translation: 提供相变存储器件及其形成方法，通过依次执行包括各向异性蚀刻工艺和各向同性蚀刻工艺的图案化处理，与最小线宽相比加宽电池孔的宽度。 掺杂剂掺杂线（110）形成在半导体衬底（100）的上表面上。 在半导体基板上形成有模具绝缘层（120）。 通过以各向异性蚀刻方法图案化模具绝缘层来形成用于暴露掺杂掺杂线的预备电池孔。 通过以各向同性方法蚀刻具有初级电池孔的模具绝缘层来形成电池孔（125a）。 在电池孔内形成二极管（130）。 在二极管上形成加热电极（140）。 在加热器电极上形成相变图案（145）。

公开(公告)号：KR100780964B1

公开(公告)日：2007-12-03

申请号：KR1020060111721

申请日：2006-11-13

Applicant: 삼성전자주식회사

Inventor： 이광우 ,  오재희 ,  정창욱

IPC: H01L27/115

CPC classification number: H01L45/144 ,  G11C13/0004 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675 ,  H01L21/76897

Abstract: A phase-change memory device having a cell diode and a manufacturing method thereof are provided to reduce the effect of a parasitic bipolar junction transistor and to minimize electrical disturbance by employing a sidewall dielectric formed on a signal line exposed to a sidewall of a cell contact hole. A signal line(WL2) that is an impurity region is arranged on a semiconductor substrate(10). A mold dielectric(18) is formed on the substrate having the signal lines. A cell contact hole(18a) passes through the mold dielectric and extended to a part of an upper portion of the signal line. A sidewall dielectric is formed on the signal line exposed to a sidewall of the cell contact hole. A vertical cell diode(D) is arranged in the cell contact hole. The sidewall dielectric is extended to be arranged on the mold dielectric exposed to the sidewall of the cell contact hole. The sidewall dielectric is a silicon oxide layer, a silicon nitride layer, or a silicon oxide nitride layer. The signal line is a first type impurity region. The vertical cell diode includes a first type semiconductor(21) and a second type semiconductor(23) that are laminated in turn.

Abstract translation: 提供具有单元二极管及其制造方法的相变存储器件，以减少寄生双极结晶体管的影响，并且通过采用形成在暴露于电池触点的侧壁的信号线上的侧壁电介质来最小化电扰动 孔。 作为杂质区域的信号线（WL2）配置在半导体基板（10）上。 在具有信号线的基板上形成模制电介质（18）。 电池接触孔（18a）穿过模具电介质并延伸到信号线的上部的一部分。 在暴露于电池接触孔的侧壁的信号线上形成侧壁电介质。 在单元接触孔中布置有垂直单元二极管（D）。 侧壁电介质被延伸以布置在暴露于电池接触孔的侧壁的模具电介质上。 侧壁电介质是氧化硅层，氮化硅层或氧化硅氮化物层。 信号线是第一类杂质区。 垂直单元二极管包括依次层叠的第一类型半导体（21）和第二类型半导体（23）。

公开(公告)号：KR1020040079523A

公开(公告)日：2004-09-16

申请号：KR1020030014414

申请日：2003-03-07

Applicant: 삼성전자주식회사

Inventor： 오재희 ,  이덕형

IPC: H01L27/108

CPC classification number: H01L27/10894 ,  H01L21/31691 ,  H01L27/10811 ,  H01L27/10885 ,  H01L28/55 ,  H01L28/65

Abstract: PURPOSE: A semiconductor device having a capacitor-under-bitline structure and a fabricating method thereof are provided to reduce the manufacturing cost by minimizing the number of lithography processes in comparison with a standard logic process. CONSTITUTION: A plurality of gate lines are formed on the first and the second regions of a semiconductor substrate(100). An insulating layer(112) is formed with a plurality of storage node contact holes(114a), a plurality of bit line contact holes(114b), gate lines of the second region, and metal contact holes(114c). A plurality of conductive plugs are formed within the storage node contact holes, the bit line contact holes, and the metal contact holes. The first metal lines(122) are formed on the insulating layer of the second region. A plurality of capacitors(132) are formed on the insulating layer of the first region. The first interlayer dielectric(120,124) is formed on the capacitor, the first metal line, and the insulating layer. The second metal lines(138b,138c) are formed on the first interlayer dielectric of the second region.

Abstract translation: 目的：提供一种具有电容器下位线结构及其制造方法的半导体器件，其与标准逻辑处理相比最小化光刻处理的数量来降低制造成本。 构成：在半导体衬底（100）的第一和第二区域上形成多条栅极线。 绝缘层（112）形成有多个存储节点接触孔（114a），多个位线接触孔（114b），第二区域的栅极线和金属接触孔（114c）。 在存储节点接触孔，位线接触孔和金属接触孔内形成多个导电插塞。 第一金属线（122）形成在第二区域的绝缘层上。 在第一区域的绝缘层上形成多个电容器（132）。 第一层间电介质（120,124）形成在电容器，第一金属线和绝缘层上。 第二金属线（138b，138c）形成在第二区域的第一层间电介质上。

公开(公告)号：KR100399769B1

公开(公告)日：2003-09-26

申请号：KR1020010012857

申请日：2001-03-13

Applicant: 삼성전자주식회사

Inventor： 오재희

IPC: H01L21/108

CPC classification number: H01L27/10894 ,  H01L27/10814 ,  H01L27/10882 ,  H01L28/90 ,  Y10S257/906 ,  Y10S257/907

Abstract: Method of fabricating a semiconductor memory device includes the steps of: forming a gate electrode on a silicon substrate; forming a first inter-layer dielectric layer (ILD1) on the silicon substrate; forming a cell pad poly between the gate electrodes in the cell area; forming a direct-contact plug (DC) on the cell pad poly in the cell area, and a first landing stud on the gate in the peripheral area; forming a bit line on the DC in the cell area and a second landing stud on the first landing stud; forming a second inter-layer dielectric layer (ILD2) on the ILD1; forming a silicon nitride layer on the ILD2; patterning the silicon nitride layer; simultaneously etching out a portion of the ILD2 in the cell area and a portion of the ILD2 and a portion of the ILD1 in the peripheral area; and simultaneously forming a plurality of buried contact plugs in the cell area and a first metal contact plug in the peripheral area.

Abstract translation: 制造半导体存储器件的方法包括以下步骤：在硅衬底上形成栅电极; 在硅衬底上形成第一层间电介质层（ILD1） 在单元区域中的栅电极之间形成单元焊盘多晶硅; 在单元区域中的单元焊盘poly上形成直接接触插塞（DC），并且在外围区域的栅极上形成第一着屏柱; 在单元区域中的DC上形成位线并在第一着陆螺柱上形成第二着陆螺柱; 在ILD1上形成第二层间电介质层（ILD2） 在ILD2上形成氮化硅层; 图案化氮化硅层; 同时蚀刻掉所述单元区域中的一部分ILD2和所述外围区域中的一部分ILD2和一部分ILD1; 并且同时在单元区域中形成多个掩埋接触塞并且在外围区域中形成第一金属接触塞。

公开(公告)号：KR1020020072846A

公开(公告)日：2002-09-19

申请号：KR1020010012857

申请日：2001-03-13

Applicant: 삼성전자주식회사

Inventor： 오재희

IPC: H01L21/108

CPC classification number: H01L27/10894 ,  H01L27/10814 ,  H01L27/10882 ,  H01L28/90 ,  Y10S257/906 ,  Y10S257/907

Abstract: PURPOSE: A semiconductor memory device of a capacitor over bit line structure having an MIM(Metal/high dielectric Insulator/Metal) capacitor and a method for fabricating the same are provided to simplify a fabrication process by performing simultaneously a metal contact forming process and a buried contact forming process. CONSTITUTION: A gate electrode(22) is formed on a semiconductor substrate(10). The first interlayer dielectric(12) is formed on the semiconductor substrate(10). The second interlayer dielectric(14) is formed on the first interlayer dielectric(12). A direct contact(30) and a bit line are formed on the second interlayer dielectric(14). A landing stud for a metal contact(28) is formed on the gate(22). A metal contact hole is formed on a peripheral region. A landing pad for a storage contact node and the metal contact hole are formed on a cell region. A metal contact(24) is formed on the peripheral region and the cell region. Si3N4(16) is deposited on the second interlayer dielectric(14). The third interlayer dielectric(18) is formed thereon. A process for forming an MIM capacitor(26) is performed. The fourth interlayer dielectric(20) is formed thereon. The metal contact(24) is patterned by a photolithography method. The metal contact(28) is opened by performing a dry etching process.

Abstract translation: 目的：提供一种具有MIM（金属/高介电绝缘体/金属）电容器的位线结构的电容器的半导体存储器件及其制造方法，以通过同时进行金属接触形成工艺和 埋地接触成型工艺。 构成：在半导体衬底（10）上形成栅电极（22）。 第一层间电介质（12）形成在半导体衬底（10）上。 第二层间电介质（14）形成在第一层间电介质（12）上。 在第二层间电介质（14）上形成直接接触（30）和位线。 在门（22）上形成用于金属接触件（28）的着陆螺柱。 金属接触孔形成在周边区域。 用于存储接触节点的接合焊盘和金属接触孔形成在电池区域上。 金属触点（24）形成在周边区域和电池区域上。 Si 3 N 4（16）沉积在第二层间电介质（14）上。 第三层间电介质（18）形成在其上。 执行用于形成MIM电容器（26）的工艺。 在其上形成第四层间电介质（20）。 通过光刻法对金属接触（24）进行构图。 通过进行干蚀刻工艺来打开金属接触件（28）。