公开(公告)号：KR100654361B1

公开(公告)日：2006-12-08

申请号：KR1020050086530

申请日：2005-09-15

Applicant: 한양대학교 산학협력단 ,  삼성전자주식회사

Inventor： 김태환 ,  김영호 ,  김재호 ,  정재훈

IPC: H01L27/115 ,  B82Y10/00

公开(公告)号：KR100643628B1

公开(公告)日：2006-11-10

申请号：KR1020050105280

申请日：2005-11-04

Applicant: 제일모직주식회사 ,  삼성전자주식회사

Inventor： 정재훈 ,  이인경 ,  최원영 ,  이태영 ,  양지철

IPC: C09K3/14

Abstract: Provided are a CMP slurry composition for polishing polycrystalline silicon which is improved in polishing uniformity and selectivity by reducing the surface defect of a wafer, and its preparation method. The CMP slurry composition comprises a metal oxide; a quaternary ammonium base compound; and 0.001-1 wt% of a fluorine-based surfactant represented by CF3(CF2)nSO2X, wherein n is 1-20; X is COOR, RO, (OCH2CH2)n' or (OCH2CH(OH)CH2)n'; R is a C1-C20 alkyl group; and n' is 1-100. Preferably the metal oxide is at least one selected from the group consisting of SiO2, Al2O3, CeO2, ZrO2 and TiO2 and has a primary particle size of 10-200 nm and a specific surface area of 10-300 m^2/g; and the quaternary ammonium base compound is at least one selected from the group consisting of tetramethylammonium hydroxide, tetraethylammonium hydroxide, tetrapropylammonium hydroxide and tetrabutylammonium hydroxide.

Abstract translation: 本发明提供一种用于抛光多晶硅的CMP浆料组合物，其通过减少晶片的表面缺陷而提高抛光均匀性和选择性，及其制备方法。 CMP浆料组合物包含金属氧化物; 季铵碱化合物; 和0.001-1重量％的由CF 3（CF 2）n SO 2 X表示的氟基表面活性剂，其中n为1-20; X是COOR，RO，（OCH 2 CH 2）n'或（OCH 2 CH（OH）CH 2）n'; R是C1-C20烷基; 和n'是1-100。 优选金属氧化物为选自SiO 2，Al 2 O 3，CeO 2，ZrO 2和TiO 2中的至少一种，其一次粒径为10-200nm，比表面积为10-300平方公尺/ g; 并且季铵碱化合物是选自氢氧化四甲基铵，氢氧化四乙基铵，氢氧化四丙基铵和氢氧化四丁基铵中的至少一种。

公开(公告)号：KR1020060108088A

公开(公告)日：2006-10-17

申请号：KR1020050030219

申请日：2005-04-12

Applicant: 한양대학교 산학협력단 ,  삼성전자주식회사

Inventor： 김태환 ,  김영호 ,  김재호 ,  정재훈

IPC: H01L27/115 ,  B82Y10/00

CPC classification number: H01L29/66825 ,  H01L21/02112 ,  H01L27/11543 ,  H01L29/788

Abstract: 터널링 절연층 위에 고분자 박막 내에 자발형성된 Ni
1-x Fe
x (0 1-x Fe
x 를 스퍼터링하는 단계, 상기 스퍼터링된 Ni
1-x Fe
x 층 상에 절연체 고분자 단량체를 포함하는 산성 전구체를 용매에 녹여 스핀 코팅하고 잔여 용매를 제거하는 단계 및 상기 코팅된 고분자 물질 내부에서 Ni
1-x Fe
x 나노결정체가 형성되도록 상기 고분자 물질에 열을 가하는 단계를 포함하는 플래쉬 메모리 소자의 제조방법에 따르면 Ni
1-x Fe
x 나노결정체의 크기와 밀도의 조절이 용이하며 이를 통하여 나노 플로팅 게이트의 성능을 향상시킬 수 있다.
플래시 메모리, 나노결정체, 플로팅 게이트, 고분자 박막, 터널링 절연층

公开(公告)号：KR1020060063439A

公开(公告)日：2006-06-12

申请号：KR1020040102615

申请日：2004-12-07

Applicant: 삼성전자주식회사

Inventor： 정재훈 ,  송두헌

IPC: H01L27/108

CPC classification number: H01L28/91 ,  H01L27/10855

Abstract: 디램의 커패시터들을 제공한다. 상기 캐패시터들은 반도체 기판 상에 반도체 제조 공정을 통해서 하부전극들이 쓰러지지 않도록 하는 방안을 제시해준다. 이를 위해서, 활성 영역의 반도체 기판 상에 두 개의 도전막 패턴들이 배치된다. 상기 도전막 패턴들의 상면들의 소정 영역들과 각각 접촉하는 하부전극들이 배치된다. 상기 도전막 패턴들의 상면들의 다른 영역들 상에 지지 패턴들이 각각 배치된다. 그리고, 상기 지지 패턴들, 도전막 패턴들 및 반도체 기판 상에 반도체 막이 덮인다.
커패시터, 하부전극, 반도체 기판.

公开(公告)号：KR1020040096719A

公开(公告)日：2004-11-17

申请号：KR1020030029624

申请日：2003-05-10

Applicant: 삼성전자주식회사 ,  주식회사 디지털앤아날로그

Inventor： 양정길 ,  정재훈 ,  조국춘

IPC: H03F3/217

CPC classification number: H03F3/217

Abstract: PURPOSE: A D-class type power amplifier for preventing an over-response phenomenon in a turning process of an abnormal state to a normal state is provided to restrain a saturation state of an integral controlling circuit or a proportional integral controlling circuit by performing a sub negative feedback loop operation. CONSTITUTION: A sum circuit(100) is used for summing up an input signal and a negative feedback signal and outputting an error signal. An integral controlling circuit(200) is used for integrating the error signal and an integral signal. A feedback controller(300) is used for outputting a switching control signal in response to a monitoring signal. A switching circuit(400) is used for receiving the integral signal and outputting the integral signal to the auxiliary loop direction or the normal state loop direction. A sub negative feedback circuit(500) is used for outputting an auxiliary negative feedback signal of negative feedback signals which are generated from an integral signal process. A controlled circuit(600) is used for modulating the integral signal to a PWM signal and outputting an output signal generated from a switching amplification process and an LPF filtering process. A steady-state negative feedback circuit(700) is used for outputting a steady-state negative feedback by processing the output signal of the controlled circuit.

Abstract translation: 目的：提供一种用于防止异常状态转为正常状态的过度响应现象的D级功率放大器，以通过执行子程序来抑制积分控制电路或比例积分控制电路的饱和状态 负反馈回路操作。 构成：求和电路（100）用于对输入信号和负反馈信号进行求和并输出误差信号。 积分控制电路（200）用于积分误差信号和积分信号。 反馈控制器（300）用于响应于监视信号输出开关控制信号。 开关电路（400）用于接收积分信号并将积分信号输出到辅助回路方向或正常状态回路方向。 子负反馈电路（500）用于输出从积分信号处理产生的负反馈信号的辅助负反馈信号。 控制电路（600）用于将积分信号调制成PWM信号并输出​​从开关放大处理和LPF滤波处理产生的输出信号。 稳态负反馈电路（700）用于通过处理受控电路的输出信号来输出稳态负反馈。

公开(公告)号：KR1020030068851A

公开(公告)日：2003-08-25

申请号：KR1020020008507

申请日：2002-02-18

Applicant: 삼성전자주식회사

Inventor： 정재훈

IPC: H04M3/22

Abstract: PURPOSE: An apparatus for managing link states of subscriber boards in a switch system is provided to easily manage the link states of the subscriber boards of the switch system by simply managing link states of standby subscriber boards. CONSTITUTION: A standby board link state monitor unit(30) monitors link states of a plurality of standby subscriber boards and outputs a plurality of second link state information. A link selecting unit(24) connects a plurality of active subscriber boards to a plurality of active board link state detecting units(26), and successively connects a plurality of the standby subscriber boards to the standby board link state monitor unit(30), by the control of a local processor unit(32). A link state managing unit(28) receives a plurality of first link state information, and transmits received first link state information to a plurality of the active subscriber boards. The link state managing unit(28) successively receives a plurality of second link state information and transmits received second link state information to a plurality of the standby subscriber boards. The local processor unit(32) receives a state conversion control signal, and controls the link selecting unit(24) so that the active subscriber boards and the standby subscriber boards connect to the active board link state detecting units(26) and the standby board link state monitor unit(30).

Abstract translation: 目的：提供一种管理交换机系统用户板链路状态的装置，通过简单管理备用用户板的链路状态，轻松管理交换机系统用户板的链路状态。 构成：备用板链路状态监视单元（30）监视多个备用用户板的链路状态，并输出多个第二链路状态信息。 链路选择单元（24）将多个活动用户板连接到多个主用板链路状态检测单元（26），并且将多个备用用户板连续地连接到备用板链路状态监视单元（30） 通过本地处理器单元（32）的控制。 链路状态管理单元（28）接收多个第一链路状态信息，并将接收到的第一链路状态信息发送到多个活动用户板。 链路状态管理单元（28）连续地接收多个第二链路状态信息，并将接收到的第二链路状态信息发送到多个备用用户板。 本地处理器单元（32）接收状态转换控制信号，并控制链路选择单元（24），使得主用用户板和备用用户板连接到主用板链路状态检测单元（26）和备用板 链路状态监视单元（30）。

公开(公告)号：KR1020030019997A

公开(公告)日：2003-03-08

申请号：KR1020010052238

申请日：2001-08-28

Applicant: 한국과학기술원 ,  삼성전자주식회사

Inventor： 박수원 ,  정재훈 ,  권재균 ,  윤지영 ,  문성호 ,  박수미 ,  성단근 ,  이주호 ,  김정곤 ,  이혜영 ,  황승오 ,  이현우

IPC: H04B7/26

CPC classification number: H04W56/0015 ,  H04B7/2687 ,  H04W88/08

Abstract: PURPOSE: A method and an apparatus for synchronizing a base station in a mobile communication system are provided to perform the synchronization of the base station by acquiring the system time difference between a primary base station and a secondary base station through a wireless link and adjusting a system time of the secondary base station. CONSTITUTION: A secondary base station judges a sign of a system time difference(641). If the sign of the system time difference is a positive number, the secondary base station moves its system time forward by a time(T track) because a system clock of the secondary base station is slower than a system clock of a primary base station(643,645,647). If the sign of the system time difference is a negative number, the secondary base station moves its system time backward by the time(T track) because the system clock of the secondary base station is faster than the system clock of the primary base station(644,646,648).

Abstract translation: 目的：提供一种用于在移动通信系统中同步基站的方法和装置，以通过无线链路获取主基站与次基站之间的系统时间差来执行基站的同步，并调整 二级基站的系统时间。 构成：辅助基站判断系统时差的符号（641）。 如果系统时间差的符号是正数，则辅助基站将其系统时间向前移动一段时间（T track），因为辅助基站的系统时钟比主基站的系统时钟慢 643645647）。 如果系统时间差的符号是负数，则辅助基站将系统时间向后移动时间（T track），因为辅助基站的系统时钟比主基站的系统时钟快 644646648）。

公开(公告)号：KR1020020006090A

公开(公告)日：2002-01-19

申请号：KR1020000039559

申请日：2000-07-11

Applicant: 삼성전자주식회사

Inventor： 이윤성 ,  정재훈

IPC: H01L21/76

Abstract: PURPOSE: A method for manufacturing a trench isolation layer of a semiconductor device is provided to prevent a gate electrode from being short-circuited by making a dented region not formed in the upper portion of a trench, and to reduce manufacturing time and cost by simplifying a manufacturing process. CONSTITUTION: A pad oxide layer is formed on a semiconductor substrate(100). A plasma-enhanced SiON(PE-SiON) layer is formed on the pad oxide layer. A photoresist pattern is formed on the PE-SiON layer to define an isolation region. The PE-SiON layer is etched by using the photoresist pattern as a mask until the pad oxide layer is exposed. After the photoresist pattern is eliminated, oxygen ions are implanted to the isolation region by using the patterned PE-SiON layer as a mask. The oxygen ions-implanted semiconductor substrate is annealed so that silicon reacts with oxygen to form the trench isolation layer(108) composed of a silicon oxide layer. The PE-SiON layer and the pad oxide layer are eliminated.

Abstract translation: 目的：提供一种制造半导体器件的沟槽隔离层的方法，以通过使沟槽的上部未形成凹陷区域来防止栅电极短路，并且通过简化制造时间和成本来减少制造时间和成本 制造过程。 构成：在半导体衬底（100）上形成衬垫氧化物层。 在衬垫氧化物层上形成等离子体增强的SiON（PE-SiON）层。 在PE-SiON层上形成光致抗蚀剂图案以限定隔离区域。 通过使用光致抗蚀剂图案作为掩模来蚀刻PE-SiON层，直到衬垫氧化物层露出。 在消除光致抗蚀剂图案之后，通过使用图案化的PE-SiON层作为掩模将氧离子注入隔离区。 氧离子注入的半导体衬底被退火，使得硅与氧气反应形成由氧化硅层构成的沟槽隔离层（108）。 PE-SiON层和衬垫氧化物层被去除。

公开(公告)号：KR1020010019352A

公开(公告)日：2001-03-15

申请号：KR1019990035707

申请日：1999-08-26

Applicant: 삼성전자주식회사

Inventor： 이영철 ,  송민규 ,  표정렬 ,  정재훈

IPC: G06F7/52

Abstract: PURPOSE: A compressor of a multiplier is provided to compress partial data additionally generated from an operation of an encoder so that it can prevent a wrong operation of the multiplier caused from the calculation of the partial data and reduce a layout area. CONSTITUTION: The compressor(300) comprises a plurality of compressors(300_1, 300_2, 300_n-1, 300n). The compression units(300_1, 300_2, 300_n-1, 300n) includes a plurality of 4 by 2 compressors(COM1, COM2, COM3, COM5) and at least one 9 by 2 compressor(COM4) and compresses the partial data(P_DATA) from the encoder(10). The compressor(300) compresses not only the partial data with a bit number set in advance by the encoder(10), but also the partial data additionally generated by a minus symbol used in a calculation process within the decoder(10).

Abstract translation: 目的：提供乘法器的压缩器来压缩从编码器的操作附加产生的部分数据，从而可以防止由于部分数据的计算引起的乘法器的错误操作并减少布局区域。 构成：压缩机（300）包括多个压缩机（300_1,300_2,300_n-1,300n）。 压缩单元（300_1,300_2,300_n-1,300n）包括多个4×2压缩机（COM1，COM2，COM3，COM5）和至少一个9×2压缩器（COM4），并压缩部分数据（P_DATA） 来自编码器（10）。 压缩器（300）不仅利用编码器（10）预先设定的位数来压缩部分数据，还压缩由解码器（10）内的计算处理中使用的减号所附加的部分数据。

公开(公告)号：KR100273967B1

公开(公告)日：2000-12-15

申请号：KR1019980013668

申请日：1998-04-16

Applicant: 삼성전자주식회사

Inventor： 정재훈

IPC: H04M3/22

Abstract: PURPOSE: A method for operating a maintenance-use dual-parallel bus in an exchange system and a system thereof are provided to enable the maintenance part to efficiently manage the status of each part, and correctly to detect the chip with error as well as to provide the system with a simplified signaling structure among a number of parts. CONSTITUTION: In a maintenance system of an exchange system consisting of a maintenance part(100) and the 1 to 12 chip blocks(CHIP0-CHIP11), the maintenance part(100) and the first chip block(CHIP0) are connected through the first bi-directional transmission-use bus(MA-BUS). The maintenance part(100) and the twelfth chip block(CHIP11) are connected through the second bi-directional transmission-use bus(MS-BUS). The first through twelfth chip blocks(CHIP0-CHIP11) are connected in series, entirely through the loop.

Abstract translation: 目的：提供一种用于在交换系统及其系统中操作维护用双平行总线的方法，以使得维护部件能够有效地管理每个部件的状态，并且正确地错误地检测芯片以及 为系统提供了许多部分之间的简化信令结构。 构成：在由维护部件（100）和1至12个芯片块（CHIP0-CHIP11）组成的交换系统的维护系统中，维护部件（100）和第一芯片块（CHIP0）通过第一 双向传输使用总线（MA-BUS）。 维护部（100）和第十二芯片块（CHIP11）通过第二双向传输用总线（MS-BUS）连接。 第一至第十二个芯片块（CHIP0-CHIP11）完全通过环路串联连接。