公开(公告)号：WO1995024768A1

公开(公告)日：1995-09-14

申请号：PCT/US1994007132

申请日：1994-06-23

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  BREWER, Robert, J.

IPC: H03H17/06

CPC classification number: H03H17/0664

Abstract: A digital filter includes a pre-filter cascaded to a low pass filter. The pre-filter has a transfer function providing generally increasing attenuation with increasing frequency above a cutoff frequency. The low pass filter has a transfer function providing substantially decreasing attenuation with increasing frequency above the cutoff frequency. The low pass filter is an FIR filter including coefficients restricted to the set (+1, 0 and -1). The filters are preferably implemented using simple hardware such as addressable read/write RAM, digital adder/subtracters, and registers. Alternatively, the addressable RAM can be replaced with shift registers. Such a filter is easily and economically implemented and has a favorable overall frequency response characteristic. The filter is, therefore, well suited for use in many digital applications and, in particular, for use as a decimation filter in an oversampled, multi-bit, high order analog-to-digital converter system.

Abstract translation: 数字滤波器包括级联到低通滤波器的预滤波器。 预滤波器具有传递函数，通过增加截止频率以上的频率提供增加的衰减。 低通滤波器具有传递函数，其在截止频率之上的频率增加时提供显着减小的衰减。 低通滤波器是包括限于集合（+1,0和-1）的系数的FIR滤波器。 滤波器优选地使用诸如可寻址读/写RAM，数字加法器/减法器和寄存器之类的简单硬件来实现。 或者，可寻址RAM可以用移位寄存器代替。 这种滤波器容易且经济地实现，并具有良好的总体频率响应特性。 因此，滤波器非常适用于许多数字应用，特别是用于过采样，多位，高阶模数转换器系统中的抽取滤波器。

公开(公告)号：WO1994008395A1

公开(公告)日：1994-04-14

申请号：PCT/US1993009329

申请日：1993-09-30

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  ADAMS, Robert, W. ,  KWAN, Tom, W. ,  COLN, Michael

IPC: H03H17/06

CPC classification number: H03H17/0628

Abstract: An asynchronous digital sample rate converter includes a random access memory (110) for storing input data values and a read only memory (104) for storing a reduced set of interpolation filter coefficients. Input data is written to the random access memory at the input sample rate. Output samples are provided from a multiply/accumulate engine which, given a stream of input data and filter coefficients, produces an output sample upon request at the output frequency. The initial address for reading input data from the random access memory, and the addresses for coefficients from the read only memory are provided by an auto-centering scheme which is a first order closed loop system with a digital integrator fed by an approximation of the input to output sample rate ratio. This auto-centering scheme may include a feed forward low pass filter to cancel steady state error, and an interpolated write address to reduce noise. A circuit determining the output to input sample rate ratios can also be provided to scale coefficient addresses and resulting output samples to allow for decimation. This circuit includes a form of digital hysteresis to eliminate noise. The ROM coefficients are reduced by relying on the symmetry of the impulse response of the interpolation filter and by utilizing a variable step size forward and backward linear interpolation.

Abstract translation: 异步数字采样率转换器包括用于存储输入数据值的随机存取存储器（110）和用于存储一组缩减的内插滤波器系数的只读存储器（104）。 输入数据以输入采样率写入随机存取存储器。 输出样本从乘法/累加引擎提供，给定输入数据流和滤波器系数，根据请求在输出频率产生输出采样。 用于从随机存取存储器读取输入数据的初始地址和来自只读存储器的系数的地址由自动定心方案提供，该自动定心方案是具有通过输入的近似馈送的数字积分器的一阶闭环系统 输出采样率。 这种自动对中方案可以包括用于消除稳态误差的前馈低通滤波器和内插的写入地址以减少噪声。 还可以提供确定输入到输入采样速率比的电路，以缩放系数地址和产生的输出采样以允许抽取。 该电路包括一种消除噪声的数字滞后形式。 通过依赖于内插滤波器的脉冲响应的对称性以及利用可变步长前后线性插值来减小ROM系数。

公开(公告)号：WO1993018573A1

公开(公告)日：1993-09-16

申请号：PCT/US1993001668

申请日：1993-03-01

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  BREWER, Robert, J.

IPC: H02M03/18

CPC classification number: H02M3/07 ,  H02M2001/009

Abstract: A charge pump circuit (10) for providing a bipolar voltage output at substantially double the unipolar voltage input source includes first and second voltage input terminals (12, 14); a first and a second capacitor (24, 26); a first switching device (30, 32, 44, 46) for selectively connecting first and second capacitors (24, 26) across the input terminals (12, 14) to charge each to the voltage of the input source; first and second voltage output terminals (16, 18); a second switching device (34, 36, 38) for selectively connecting the capacitors (24, 26) in series between one of the input terminals (14) and one of the output terminals (18) to generate a first polarity voltage (-2V) which is substantially double the voltage of the input source; a third switching device (40, 42) for selectively connecting at least one of the capacitors (24) in series between the other of the input terminals (12) and the other of the output terminals (16) to generate a second polarity voltage (+2V) which is substantially double the voltage of the input source; and a clock for sequentially, selectively actuating the first (30, 32, 44, 46), second (34, 36, 38) and third (40, 42) switching devices.

公开(公告)号：WO1993018552A1

公开(公告)日：1993-09-16

申请号：PCT/US1993002148

申请日：1993-03-10

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  DOS SANTOS, Francisco, Jr. ,  DEVITO, Larry, M.

IPC: H01L29/08

CPC classification number: H01L27/0821

Abstract: An integrated circuit including a semiconductor substrate, a semiconductor layer formed on the substrate, a desired bipolar transistor formed in the semiconductor layer. First and second parasitic elements are formed in the integrated circuit. An element is provided which detects when the second parasitic element becomes active or which prevents increase of the collector-to-emitter voltage of the desired bipolar transistor in response to current flowing through the second parasitic transistor. This element may be a semiconductor region formed in the semiconductor layer. The transistor may be an npn or pnp type transistor manufactured according to a complementary bipolar process or other process which results in a transistor with first and second parasitic elements. The present invention is also well-suited for use in the output stage of an operational amplifier. The element which detects activity of the second parasitic transistor intercepts carriers flowing towards the junction isolation bands and substrate from the collector of the desired bipolar transistor.

Abstract translation: 一种集成电路，包括半导体衬底，形成在衬底上的半导体层，形成在半导体层中的所需双极晶体管。 第一和第二寄生元件形成在集成电路中。 提供了一种元件，其检测第二寄生元件什么时候变为有效或者防止响应于流过第二寄生晶体管的电流而增加期望的双极晶体管的集电极 - 发射极电压。 该元件可以是形成在半导体层中的半导体区域。 晶体管可以是根据互补双极性工艺或其它工艺制造的npn或pnp型晶体管，其导致具有第一和第二寄生元件的晶体管。 本发明也适用于运算放大器的输出级。 检测第二寄生晶体管的活性的元件截取从所需双极晶体管的集电极流向结隔离带和衬底的载流子。

公开(公告)号：WO1992014301A1

公开(公告)日：1992-08-20

申请号：PCT/US1992001092

申请日：1992-02-11

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  GANESAN, Apparajan ,  FERGUSON, Paul F., Jr. ,  ROBERTSON, David H.

IPC: H03F03/45

CPC classification number: H03F1/3211 ,  H03F1/223 ,  H03F3/45076

Abstract: Gain linearity problems caused by impact ionization in an active MOS device are avoided by connecting an MOS shield device in series with the active MOS device so that the overall supply voltage is split across two devices, keeping both devices in a region of operation well below where impact ionization becomes a significant problem. The gate of the MOS shield device is maintained at a voltage proportional to its drain voltage, thereby keeping the device in the saturation mode and avoiding an abrupt mode change associated with prior art shield circuits.

Abstract translation: 通过将MOS屏蔽器件与有源MOS器件串联连接来避免在有源MOS器件中产生的冲击电离引起的增益线性问题，使得整个电源电压在两个器件之间分离，从而将两个器件保持在低于 冲击电离成为一个重大问题。 MOS屏蔽器件的栅极保持与其漏极电压成比例的电压，从而保持器件处于饱和模式，并避免与现有技术的屏蔽电路相关的突然模式变化。

公开(公告)号：WO1992009025A2

公开(公告)日：1992-05-29

申请号：PCT/US1991008188

申请日：1991-11-04

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  GARDE, Douglas

IPC: G06F0

CPC classification number: G06F9/30141 ,  G11C7/1006 ,  G11C7/1078 ,  G11C8/16

Abstract: A multi-port RAM register file adapted for flowing data directly from an input port of the register file to an output port of the register file and for simultaneously writing to a memory location in the register file. In addition to the RAM register, the apparatus includes, in a first embodiment, (1) first and second sets of multiplexers, the first set of multiplexers connected between the register file output ports on the one hand, and, on the other hand, the outputs of the second set of multiplexers and the RAM bit lines; the second set of multiplexers being connected between one input of the first set of multiplexers, as aforementioned, and the RAM register file input ports; and (3) flow-through address comparators for controlling the multiplexers. The bit buses of the RAM are driven directly from the register file input ports. In a second embodiment, the first and second multiplexers are combined, with the outputs of the RAM bit lines being connected to inputs of the combined multiplexer, and with the combined multiplexer forming a crossbar switch.

公开(公告)号：WO1992008186A1

公开(公告)日：1992-05-14

申请号：PCT/US1991008102

申请日：1991-11-01

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  GARDE, Douglas

IPC: G06F05/06

CPC classification number: G06F5/10 ,  G06F7/72 ,  G06F9/3552 ,  G06F2205/106

Abstract: The invention comprises a hardware constructed address generator for a circular buffer which can be of any size and be in any position in memory. The address generator calculates both an absolute value and a wrapped value and selects one in accordance with whether the wrapped value falls within the boundaries of the buffer.

Abstract translation: 本发明包括用于圆形缓冲器的硬件构造的地址发生器，其可以是任何大小并且在存储器中的任何位置。 地址生成器计算绝对值和包装值，并根据包装值是否落在缓冲区的边界内选择一个。

公开(公告)号：WO1991014946A1

公开(公告)日：1991-10-03

申请号：PCT/US1991002095

申请日：1991-03-27

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  WEBB, Spencer, L.

IPC: G01R33/04

CPC classification number: G01R33/04

Abstract: The effects of non-equal saturation spikes in a magnetic oscillator magnetometer utilizing a magnetic core sensing inductor are compensated by adding the average inductor current to both the high and low current magnitude limits. In particular, each of the current limits is selected to be a fixed current (which is greater than that required to saturate the core) offset by the average current flowing in the core. The effects of magnetic core hysteresis and series resistance between the inductor and its drive sources are compensated by controlling the drive voltage levels so that the time during which the inductor is driven by current in one direction is equal to the time during which it is driven by current in the other direction.

公开(公告)号：WO1991005409A2

公开(公告)日：1991-04-18

申请号：PCT/US1990005472

申请日：1990-09-26

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  ROBERTSON, David, H. ,  REAL, Peter ,  MANGELSDORF, Christopher, W.

IPC: H03M01/16

CPC classification number: H03M1/129 ,  H03M1/168

Abstract: A pipelined multi-stage ADC in which residue signals are passed between stages as currents. All sample-and-hold circuits are designed to be current-in/current-out structures; all but one also provide a voltage output. A voltage representation of the analog signal is provided as input to the flash converter within the quantization loop of each stage, allowing implementation of a conventional voltage comparator architecture in the flash converter. An extra comparator is added to the flash converter and an extra segment is included in the DAC of each stage. Inputs above full scale and below zero can be converted and generate output codes. Whenever the input goes above full scale or below zero, an out-of-range bit is set and the digital outputs are set to all ones or all zeroes, respectively. The combination of out-of-range bit and digital codes tell whether overranging or underranging occurred.

公开(公告)号：WO1991004495A1

公开(公告)日：1991-04-04

申请号：PCT/US1990005403

申请日：1990-09-21

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  BROKAW, A., Paul

IPC: G01R19/165

CPC classification number: G01R19/16571 ,  B60Q11/00 ,  G01F23/38 ,  G01R19/32

Abstract: An apparatus for monitoring current through a lamp circuit that uses a series resistance shunt in the circuit with one end being connected to a current source and the second end being connected to the lamp. The circuitry includes a comparator that is connected across the shunt and has a threshold switching voltage such that a voltage across the shunt that is larger than the threshold voltage will switch the comparator on (as in the case where the lamp is not functioning) and a voltage across the shunt that is smaller than the threshold voltage (as in the case where the lamp is in the circuit and functioning) will switch the comparator off. In a preferred embodiment, the shunt is actually a portion of the printed circuit board trace. In order to compensate for changes in resistance in the shunt that occur as the temperature of the printed circuit board trace changes, temperature compensation circuitry is included to maintain the threshold switching voltage in a fixed relationship with the temperature of the shunt. The apparatus incorporates additional circuitry connected to the comparator in order to decrease the sensitivity of the comparator to changes in the circuit supply voltage. In a preferred embodiment, the circuit has a 50 % sensitivity to supply voltage changes. The circuit may be manufactured in monolithic integrated circuit form in order to enhance reliability, cost, and manufacturability.