公开(公告)号：US20210183918A1

公开(公告)日：2021-06-17

申请号：US16713423

申请日：2019-12-13

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： John J. Ellis-Monaghan ,  Steven M. Shank ,  Vibhor Jain ,  Anthony K. Stamper ,  John J. Pekarik

IPC: H01L27/146

Abstract: Structures including a photodiode and methods of fabricating such structures. A trench extends from a top surface of a substrate to a depth into the substrate. The photodiode includes an active layer positioned in the trench. Trench isolation regions, which are located in the substrate, are arranged to surround the trench. A portion of the substrate is positioned in a surrounding relationship about the active layer and between the active layer and the trench isolation regions.

公开(公告)号：US12170313B2

公开(公告)日：2024-12-17

申请号：US18324637

申请日：2023-05-26

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor Jain ,  Anthony K. Stamper ,  John J. Ellis-Monaghan ,  Steven M. Shank ,  Rajendran Krishnasamy

IPC: H01L29/06 ,  H01L21/763 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66 ,  H01L29/737

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich region and methods of manufacture. The structure includes: a trap rich isolation region embedded within the bulk substrate; and a heterojunction bipolar transistor above the trap rich isolation region, with its sub-collector region separated by the trap rich isolation region by a layer of the bulk substrate.

公开(公告)号：US20240243175A1

公开(公告)日：2024-07-18

申请号：US18098188

申请日：2023-01-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： Venkata Narayana Rao Vanukuru ,  Steven M. Shank

IPC: H01L29/10 ,  H01L21/74 ,  H01L27/12

CPC classification number: H01L29/1087 ,  H01L21/743 ,  H01L27/1203

Abstract: Structures including a field-effect transistor field-effect and methods of forming a structure including a field-effect transistor. The structure comprises a trench isolation region in a substrate, and a body contact region that extends through the trench isolation region to the substrate. The structure further comprises a field-effect transistor including a gate connector, a first gate finger that extends from the gate connector, a second gate finger that extends from the gate connector, and a source/drain region disposed between the first gate finger and the second gate finger. The gate connector is positioned over the trench isolation region. The structure further comprises a gate contact coupled to the gate connector, and a body contact that penetrates through a portion of the gate connector to the body contact region.

公开(公告)号：US12027553B2

公开(公告)日：2024-07-02

申请号：US17896401

申请日：2022-08-26

Applicant: GlobalFoundries U.S. Inc.

Inventor： Siva P. Adusumilli ,  Vibhor Jain ,  Alvin J. Joseph ,  Steven M. Shank

IPC: H01L27/146

CPC classification number: H01L27/14629 ,  H01L27/1462 ,  H01L27/1463 ,  H01L27/14685

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photodetectors with buried airgap mirror reflectors. The structure includes a photodetector and at least one airgap in a substrate under the photodetector.

公开(公告)号：US11880065B2

公开(公告)日：2024-01-23

申请号：US17588470

申请日：2022-01-31

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian ,  Steven M. Shank ,  Takako Hirokawa

IPC: G02B6/12 ,  G02B6/13 ,  G02B6/293

CPC classification number: G02B6/12007 ,  G02B6/13 ,  G02B6/29338

Abstract: Structures including an edge coupler and methods of fabricating a structure including an edge coupler. The structure includes an edge coupler having a longitudinal axis, a first ring resonator, and a second ring resonator. The first ring resonator has a first center point that is spaced from the longitudinal axis of the edge coupler by a first perpendicular distance. The second ring resonator has a second center point that is spaced from the longitudinal axis of the edge coupler by a second perpendicular distance.

公开(公告)号：US11822122B2

公开(公告)日：2023-11-21

申请号：US17462491

申请日：2021-08-31

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Yusheng Bian ,  Ajey Poovannummoottil Jacob ,  Steven M. Shank

IPC: G02B1/00 ,  G02B6/122 ,  G02B6/125 ,  G02B6/12

CPC classification number: G02B6/1225 ,  G02B1/002 ,  G02B1/005 ,  G02B6/125 ,  G02B2006/1213 ,  G02B2006/12061 ,  G02B2006/12147

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to waveguide structures with metamaterial structures and methods of manufacture. The structure includes: at least one waveguide structure; and metamaterial structures separated from the at least one waveguide structure by an insulator material, the metamaterial structures being structured to decouple the at least one waveguide structure to simultaneously reduce insertion loss and crosstalk of the at least one waveguide structure.

公开(公告)号：US20230317869A1

公开(公告)日：2023-10-05

申请号：US17709181

申请日：2022-03-30

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Rajendran Krishnasamy ,  John J. Ellis-Monaghan ,  Siva P. Adusumilli ,  Ramsey Hazbun ,  Steven M. Shank

IPC: H01L31/105 ,  H01L31/0224 ,  H01L31/18

CPC classification number: H01L31/105 ,  H01L31/022408 ,  H01L31/1812

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photodiodes and methods of manufacture. The structure includes: a top terminal; an intrinsic material in contact with the top terminal; and a bottom terminal in contact with the intrinsic material, the bottom terminal including a P semiconductor material and a fully depleted N semiconductor material.

公开(公告)号：US11764225B2

公开(公告)日：2023-09-19

申请号：US17344391

申请日：2021-06-10

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. Stamper ,  Uzma Rana ,  Siva P. Adusumilli ,  Steven M. Shank

IPC: H01L27/12 ,  H01L29/45 ,  H01L21/84 ,  H01L21/28 ,  H01L21/285 ,  H01L29/49

CPC classification number: H01L27/1203 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/84 ,  H01L29/45 ,  H01L29/4933

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors and methods of manufacture. The structure includes: at least one gate structure comprising source/drain regions; and at least one isolation structure perpendicular to the at least one gate structure and within the source/drain regions.

公开(公告)号：US11749559B2

公开(公告)日：2023-09-05

申请号：US17983436

申请日：2022-11-09

Applicant: GlobalFoundries U.S. Inc.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  Ian McCallum-Cook ,  Siva P. Adusumilli

IPC: H01L21/763 ,  H01L29/06 ,  H01L27/12 ,  H01L21/762 ,  H01L21/324 ,  H01L21/84 ,  H01L21/265 ,  H01L21/74 ,  H01L29/32 ,  H01L21/02 ,  H01L27/06 ,  H01L29/10

CPC classification number: H01L21/763 ,  H01L21/26506 ,  H01L21/26526 ,  H01L21/26533 ,  H01L21/324 ,  H01L21/743 ,  H01L21/76267 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/32 ,  H01L21/0217 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02271 ,  H01L27/0629 ,  H01L29/1087

Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.

公开(公告)号：US20230273369A1

公开(公告)日：2023-08-31

申请号：US17680421

申请日：2022-02-25

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh Mani Pandey ,  Yusheng Bian ,  Steven M. Shank ,  Judson Holt

IPC: G02B6/122 ,  H01L21/84 ,  G02B6/136

CPC classification number: G02B6/122 ,  G02B6/136 ,  H01L21/84

Abstract: Photonics structures including an optical component and methods of fabricating a photonics structure including an optical component. The photonics structure includes an optical component, a substrate having a cavity and a dielectric material in the cavity, and a dielectric layer positioned in a vertical direction between the optical component and the cavity. The optical component is positioned in a lateral direction to overlap with the cavity in the substrate.