公开(公告)号：DK189789A

公开(公告)日：1989-11-27

申请号：DK189789

申请日：1989-04-19

Applicant: IBM

Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G06F12/08 ,  G06F13/00 ,  G06F12/00

Abstract: A microcomputer system includes a microprocessor, a cache memroy, and a cache controller all coupled to a local bus. The local bus is coupled to a sytem bus, connecting the remaining system components, through latches. When writing data, the microcomputer can perform a posted write to a unit on the system bus by writing the data into the latches and then, on receipt of a ready signal from the cache controller, continuing its operations without waiting for the data to pas to its destination. A problem arises if the data is posted to a unit with a data width less than that of the microprocessor. In this case, the data should be sent in multiple cycles, but the read signal is generated before the data width of the unit is known and the microprocessor then continues its operations and can not, therefore, transmit the data correctly. To solve this problem, a logic unit is added to monitor the ready signal and the output of a decoder which detects non-cacheable addresses (which are of data width different from the microprocessor data width). If a non-cacheable address is detected, the read signal from the cache controller through the logic unit is withheld from the microprocessor, which now waits to continue processing beyond the write until a ready signal is received from the addressed unit on the system bus.

公开(公告)号：DK189489A

公开(公告)日：1989-11-27

申请号：DK189489

申请日：1989-04-19

Applicant: IBM

Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G06F9/38 ,  G06F12/08 ,  G06F12/00 ,  G06F13/00

Abstract: In a microcomputer system comprising a microprocessor and a cache subsystem and operable in a pipelined mode, there is potential incompatibility between pipelined operations and dynamic bus sizing as the cache subsystem operates with a fixed size data width and dynamic bus sizing allows the system to operate with devices of differing data width. This incompatibility is accommodated by the present system by defining certain addresses as cacheable addresses and other addresses as non-cacheable addresses and ensuring that addresses of devices of data width different from the cache data width are non-cacheable. An address decoder provides a control signal indicating whether or not a generated address is within the cacheable range. This control signal controls a next address signal applied to the microprocessor, which signal allows the processor to proceed to a following cycle prior to the end of the current cycle. Whenever a non-cacheable address is detected, the next address signal is suppressed.

公开(公告)号：DK189689D0

公开(公告)日：1989-04-19

申请号：DK189689

申请日：1989-04-19

Applicant: IBM

Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G06F12/08 ,  G06F13/00 ,  G06F12/00

Abstract: In a dual bus microcomputer system using a cache memory and a cache controller, the timing requirements placed on non-cache memory components by the cache controller are more stringent than the timing requirements placed on the non-cache memory components by the microprocessor. A logic circuit operates on the cache write enable (CWE) signals, and delays those signals in the event of a cache read miss. Delaying the CWE signals relaxes the timing requirements placed on non-cache memory components and at the same time does not impact wait state parameters for read miss operations.

公开(公告)号：FI891788A0

公开(公告)日：1989-04-14

申请号：FI891788

申请日：1989-04-14

Applicant: IBM

Inventor： BEGUN RALPH MURRAY ,  DEAN MARK EDWARD ,  BLAND PATRICK MAURICE

IPC: G06F12/08 ,  G06F

Abstract: In a dual bus microcomputer system using a cache memory and a cache controller, the timing requirements placed on non-cache memory components by the cache controller are more stringent than the timing requirements placed on the non-cache memory components by the microprocessor. A logic circuit operates on the cache write enable (CWE) signals, and delays those signals in the event of a cache read miss. Delaying the CWE signals relaxes the timing requirements placed on non-cache memory components and at the same time does not impact wait state parameters for read miss operations.

公开(公告)号：MX158687A

公开(公告)日：1989-02-27

申请号：MX20440585

申请日：1985-02-22

Applicant: IBM

Inventor： DEAN MARK EDWARD

IPC: G11C11/24 ,  G11C11/406 ,  G06F12/00 ,  G11B15/03

Abstract: A refresh generator system (5) for a dynamic memory (3) in a data processing system, including a processor (1) which is responsive to a hold request signal (HRQ) to relinquish control of the local bus and generate a hold acknowledge signal (HLDA), comprises logic means (14,11.10,13) to generate a hold request signal in response to an output from a refresh timer circuit (6). A logic circuit (16) is responsive to a hold request, a corresponding hold acknowledge, and the timer signal to generate a refresh control signal (REFR). This signal generates a refresh signal for the memory control circuits, increments a counter circuit (19) and initiates operation of a sequencer circuit (22). The sequencer then gates the output of the counter circuit to provide a memory row address and thereafter provides a memory read output (-MEMR) to refresh the memory row defined by the address and lastly resets the circuit to terminate the hold request signal.

公开(公告)号：DE3567115D1

公开(公告)日：1989-02-02

申请号：DE3567115

申请日：1985-01-11

Applicant: IBM

Inventor： DEAN MARK EDWARD ,  MOELLER DENNIS LEE

IPC: G06F13/28

Abstract: A microcomputer system includes a main processor (1), a memory (3) and a direct memory access controller (DMA;4) effective to control direct data transfer between the memory and input / output devices on channels. Bus control for data transfer is switchable between the DMA and processor by a hold request/acknowledge handshaking sequence between the DMA and processor. A control line (27) from the channels is activated by a peripheral processing device on a channel when it wishes to gain control of the busses for data transfer. Logic means co-act with the handshaking sequence to determine which device gains control of the busses. This logic is responsive to the DMA address enable output (AEN), the hold acknowledge output of the main processor (HLDA) and the channel control line output (-MASTER). When all these are deactivated, control passes to the main processor, when AEN and HLDA only are activated, control passes to the DMA controller and, when all three are activated, control passes to the peripheral processing device.

公开(公告)号：AT39581T

公开(公告)日：1989-01-15

申请号：AT85100105

申请日：1985-01-11

Applicant: IBM

Inventor： DEAN MARK EDWARD ,  MOELLER DENNIS LEE

IPC: G06F13/28

Abstract: A microcomputer system includes a main processor (1), a memory (3) and a direct memory access controller (DMA;4) effective to control direct data transfer between the memory and input / output devices on channels. Bus control for data transfer is switchable between the DMA and processor by a hold request/acknowledge handshaking sequence between the DMA and processor. A control line (27) from the channels is activated by a peripheral processing device on a channel when it wishes to gain control of the busses for data transfer. Logic means co-act with the handshaking sequence to determine which device gains control of the busses. This logic is responsive to the DMA address enable output (AEN), the hold acknowledge output of the main processor (HLDA) and the channel control line output (-MASTER). When all these are deactivated, control passes to the main processor, when AEN and HLDA only are activated, control passes to the DMA controller and, when all three are activated, control passes to the peripheral processing device.

公开(公告)号：DE3278546D1

公开(公告)日：1988-06-30

申请号：DE3278546

申请日：1982-07-23

Applicant: IBM

Inventor： SAENZ JESUS ANDRES ,  DEAN MARK EDWARD ,  KUMMER DAVID ALLEN

IPC: G09G5/02 ,  G09G1/28

公开(公告)号：AU567767B2

公开(公告)日：1987-12-03

申请号：AU3409984

申请日：1984-10-10

Applicant: IBM

Inventor： DEAN MARK EDWARD ,  MOELLER DENNIS LEE

IPC: G06F9/46 ,  G06F9/38 ,  G06F11/00 ,  G06F11/07 ,  G06F13/36 ,  G06F15/16 ,  G06F15/177

Abstract: In a data processing system including a main processor (1) and a co-processor (2), a logic circuit (6) is coupled to receive error and busy outputs of the co-processor to generate an interrupt output on co-incidence of active error and busy signals and to latch the busy signal to the main processor to ensure that the main processor will honour the interrupt before executing another co-processor instruction.

公开(公告)号：BR8406635A

公开(公告)日：1985-10-15

申请号：BR8406635

申请日：1984-12-20

Applicant: IBM

Inventor： DEAN MARK EDWARD ,  MOELLER DENNIS LEE

IPC: G06F9/46 ,  G06F9/38 ,  G06F11/00 ,  G06F11/07 ,  G06F13/36 ,  G06F15/16 ,  G06F15/177

Abstract: In a data processing system including a main processor (1) and a co-processor (2), a logic circuit (6) is coupled to receive error and busy outputs of the co-processor to generate an interrupt output on co-incidence of active error and busy signals and to latch the busy signal to the main processor to ensure that the main processor will honour the interrupt before executing another co-processor instruction.