公开(公告)号：EP0085048A4

公开(公告)日：1986-01-07

申请号：EP81902344

申请日：1981-08-12

Applicant: IBM

Inventor： EGGEBRECHT LEWIS CLARK ,  KUMMER DAVID ALLEN

IPC: G06F12/06 ,  G06F9/06

CPC classification number: G06F12/0623

Abstract: The extension of the size of memory, through the use of page signals in addressing such memory in previous inventions, made no provision for the possibility that a plurality of direct storage access channels which can operate simultaneously would be directed to the same extended addressing region of such storage. In order to provide for such access by the channels, this invention is directed to a computing system storage addressing apparatus (20, 40) which extends the addressing capability of an address bus (12) to enable direct storage (memory) storage access (DMA) channels (32, 33, 34 and 35), to operate simultaneously in the same or different storage pages. The computing system includes a processor (10), a plurality of storage devices (16), a data bus (14) and an address bus (12) interconnecting the processor and the storage devices, a DMA device (20) controls connection of the plurality of DMA channels to the address bus and data bus, a plurality of address registers (40) store page address signals loaded from the processor, and the address bus page address signals from an address register corresponding to a currently active DMA channel are gated to the address bus.

公开(公告)号：HK81790A

公开(公告)日：1990-10-19

申请号：HK81790

申请日：1990-10-11

Applicant: IBM

Inventor： KUMMER DAVID ALLEN

IPC: G06F3/12 ,  G06F3/153 ,  G06F12/00 ,  G06F12/06 ,  G06F13/00 ,  G06K15/00 ,  H04N9/00

Abstract: A microcomputer includes a main memory system which is accessed, substantially independently, by the CPU and a subsystem, for example a video display subsystem (12,11). The memory system comprises a base memory (22) and an optional add-ori expansion memory (42). When only the base memory is installed, consecutive locations have consecutively numbered addresses, and both the CPU and subsystem access individual locations. When both memories are installed, one has even numbered addresses and the other odd numbered addresses. With both memories installed, the CPU still accesses individual locations, but the subsystem addresses even addresses to obtain, for each access, data from the even address and the next higher odd address, thereby accessing a location in both memories. Thus the memory bandwith for the subsystem is effectively doubled when the expansion memory is installed.

公开(公告)号：AT57034T

公开(公告)日：1990-10-15

申请号：AT84107798

申请日：1984-07-05

Applicant: IBM

Inventor： KUMMER DAVID ALLEN ,  RACKLEY DARWIN PRESTON ,  SAENZ JESUS ANDRES

IPC: G09G1/06 ,  G09G1/16 ,  G09G5/00 ,  G09G5/40

Abstract: @ A raster scan display system includes a plurality of storage maps (MAPO to MAP4). These maps are addressable in either of two modes. In the first mode each map contains bit mapped data and the maps are addressed together to provide colour signals from which colour video signals are derived. In the second mode, one map contains character representing data and a further map, character display dot patterns. In this mode the first map is addressed to provide partial addresses for the further map. These partial addresses are combined with row scan data signals to access the further map from which the character display dot data is used to generate the video signals.

公开(公告)号：DE3480965D1

公开(公告)日：1990-02-08

申请号：DE3480965

申请日：1984-07-05

Applicant: IBM

Inventor： KUMMER DAVID ALLEN ,  SAENZ JESUS ANDRES ,  TRYNOSKY STEPHEN WAYNE

IPC: G09G5/00 ,  G06F3/00 ,  G06F3/14 ,  G06F7/02 ,  G06T7/00 ,  G09G1/16 ,  G09G5/02 ,  G09G5/393 ,  G09G5/395 ,  G06F15/70

Abstract: In a bit mapped raster scan digital display system, a number of maps (MAPO-MAP3), each contain a single component of the display data and are read together to provide sets of bytes, each set representing eight pel defining groups. A compare system is provided for determining when a pel group in a set of bytes compares with a reference pel defining group. For the, or each, pair of maps, the compare system compares each bit of the two bytes of data with the correspondingly positioned bit of the reference group to provide outputs when a corresponding bit in each of the bytes compares with the two reference bits. When more than two maps are employed the compare outputs related to all of the pairs of maps are combined to provide an output signal when a pel group in a byte from the maps compares with the reference bits. In a modification of the system, the comparison can be made between one or more of the maps and the corresponding bit or bits of the compare data.

公开(公告)号：AU569312B2

公开(公告)日：1988-01-28

申请号：AU3137284

申请日：1984-08-01

Applicant: IBM

Inventor： KUMMER DAVID ALLEN

IPC: G06F12/02 ,  G06F3/153 ,  G06F12/06 ,  G06F13/16 ,  G06F9/22 ,  G11C8/00

Abstract: In a microcomputer system having a main memory accessed by both a central processor unit (20) and a CRT controller (21), a page register system (30) receives page bits defining both CPU and CRT pages from CPU. The CPU page bits are combined with lower order address bits from CPU for CPU access cycles, and CRT page bits are combined with lower order address bits from CRT controller for CRT access cycles. Both CPU and CRT controller can access any of pages in memory. For compatibility with higher level systems, the CPU may provide addresses in a range outside range of addresses for memory. When a decoder (42) detects such addresses, it directs CPU address bits, corresponding in order to CPU page bits issued by the register system, to address memory.

公开(公告)号：BR8403981A

公开(公告)日：1985-07-09

申请号：BR8403981

申请日：1984-08-09

Applicant: IBM

Inventor： KUMMER DAVID ALLEN

IPC: G06F12/02 ,  G06F3/153 ,  G06F12/06 ,  G06F13/16 ,  G09G1/02

Abstract: In a microcomputer system having a main memory accessed by both a central processor unit (20) and a CRT controller (21), a page register system (30) receives page bits defining both CPU and CRT pages from CPU. The CPU page bits are combined with lower order address bits from CPU for CPU access cycles, and CRT page bits are combined with lower order address bits from CRT controller for CRT access cycles. Both CPU and CRT controller can access any of pages in memory. For compatibility with higher level systems, the CPU may provide addresses in a range outside range of addresses for memory. When a decoder (42) detects such addresses, it directs CPU address bits, corresponding in order to CPU page bits issued by the register system, to address memory.

公开(公告)号：ZA8405185B

公开(公告)日：1985-03-27

申请号：ZA8405185

申请日：1984-07-05

Applicant: IBM

Inventor： KUMMER DAVID ALLEN ,  WEBB GARY EDWARD

IPC: G11C17/00 ,  G06F9/04 ,  G06F12/06 ,  G06F13/00 ,  G06F17/00 ,  G11C5/00 ,  G06C

CPC classification number: G06F12/0638

公开(公告)号：BR8401006A

公开(公告)日：1984-10-16

申请号：BR8401006

申请日：1984-03-01

Applicant: IBM

Inventor： BREWER JAMES ARTHUR ,  KUMMER DAVID ALLEN ,  LANGGOOD JOHN KENNEDY

IPC: H05K1/00 ,  H05K1/02 ,  H05K7/02 ,  H01L23/50

Abstract: A six-layer printed circuit card has first, third and sixth layers which are signal carrying layers for interconnecting various components forming a personal computer. The second and fifth layers are both ground plane layers and the fourth layer of the card is a voltage plane. The components on the printed circuit card include eight input/output (I/O) connectors J1 - J8 to which eight other cards controlling various I/O devices can be connected. Seven of the eight I/O connectors are interconnected to a conventional I/O bus. The eighth connector J8 is interconnected to some lines of the I/O bus and to some lines of the signal carrying layers which form an internal bus.

公开(公告)号：GB2105156A

公开(公告)日：1983-03-16

申请号：GB8222694

申请日：1982-08-06

Applicant: IBM

Inventor： DEAN MARK EDWARD ,  SAENZ JESUS ANDRES ,  EGGEBRECHT LEWIS CLARK ,  KUMMER DAVID ALLEN

IPC: G09G5/02 ,  G09G1/16

Abstract: A central processing unit (10) loads a border register (36) with four color bits representing digital color signals to be used in determining the color of only the border area surrounding the video area of a cathode ray tube display screen (14). A BORDER CONTROL TIME signal is generated at the appropriate times in the horizontal and vertical scanning periods of the cathode ray tube to apply the digital color border signal (R, G, B, I) through multiplexer (32) to a composite video signal generator (38) which generates the composite video signal for a TV set (14) or a TV monitor.

公开(公告)号：HK10791A

公开(公告)日：1991-02-13

申请号：HK10791

申请日：1991-02-06

Applicant: IBM

Inventor： KUMMER DAVID ALLEN

IPC: G06F3/153 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16

Abstract: In a microcomputer system having a main memory accessed by both a central processor unit (20) and a CRT controller (21), a page register system (30) receives page bits defining both CPU and CRT pages from CPU. The CPU page bits are combined with lower order address bits from CPU for CPU access cycles, and CRT page bits are combined with lower order address bits from CRT controller for CRT access cycles. Both CPU and CRT controller can access any of pages in memory. For compatibility with higher level systems, the CPU may provide addresses in a range outside range of addresses for memory. When a decoder (42) detects such addresses, it directs CPU address bits, corresponding in order to CPU page bits issued by the register system, to address memory.