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公开(公告)号：HK4290A
公开(公告)日：1990-01-25
申请号：HK4290
申请日：1990-01-18
Applicant: IBM
Inventor： SAENZ JESUS ANDRES , DEAN MARK EDWARD , KUMMER DAVID ALLEN
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公开(公告)号：MX157248A
公开(公告)日：1988-11-08
申请号：MX20130984
申请日：1984-05-10
Applicant: IBM
Inventor： KUMMER DAVID ALLEN , SAENZ JESUS ANDRES , TRYNOSKY STEPHEN WAYNE
IPC: G09G5/00 , G06F3/00 , G06F3/14 , G06F7/02 , G06T7/00 , G09G1/16 , G09G5/02 , G09G5/393 , G09G5/395 , G11C11/067
Abstract: In a bit mapped raster scan digital display system, a number of maps (MAPO-MAP3), each contain a single component of the display data and are read together to provide sets of bytes, each set representing eight pel defining groups. A compare system is provided for determining when a pel group in a set of bytes compares with a reference pel defining group. For the, or each, pair of maps, the compare system compares each bit of the two bytes of data with the correspondingly positioned bit of the reference group to provide outputs when a corresponding bit in each of the bytes compares with the two reference bits. When more than two maps are employed the compare outputs related to all of the pairs of maps are combined to provide an output signal when a pel group in a byte from the maps compares with the reference bits. In a modification of the system, the comparison can be made between one or more of the maps and the corresponding bit or bits of the compare data.
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公开(公告)号：AU3137484A
公开(公告)日：1985-02-21
申请号：AU3137484
申请日：1984-08-01
Applicant: IBM
Inventor： KUMMER DAVID ALLEN , SAENZ JESUS ANDRES , TRYNOSKY STEPHEN WAYNE
Abstract: In a raster scan digital display system, a display image is stored, as coded characters or a bit map, which is larger than the display image. In order to define an image, within the stored image, for display, the addressing system for the memory (or memories) storing the image include a display image defining circuit. This circuit includes an address counter which is incremented to define successive addresses of data in a line of the displayed image, or row of characters therein. The circuit includes a first register to receive the initial address of a display image and a second register to receive a value indicating the width of the stored image. For the initial line (or character row) of a displayed image, the address counter is loaded from the first register and incremented from the initial address. For each subsequent line (or character row) the address from which the counter is incremented is the sum of the initial address of the previous line (or character row) and the value in the second register.
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公开(公告)号：AU3180084A
公开(公告)日：1985-02-14
申请号：AU3180084
申请日：1984-08-10
Applicant: IBM
Inventor： KUMMER DAVID ALLEN , RACKLEY DARWIN PRESTON , SAENZ JESUS ANDRES
Abstract: @ A raster scan display system includes a plurality of storage maps (MAPO to MAP4). These maps are addressable in either of two modes. In the first mode each map contains bit mapped data and the maps are addressed together to provide colour signals from which colour video signals are derived. In the second mode, one map contains character representing data and a further map, character display dot patterns. In this mode the first map is addressed to provide partial addresses for the further map. These partial addresses are combined with row scan data signals to access the further map from which the character display dot data is used to generate the video signals.
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公开(公告)号：PH26752A
公开(公告)日：1992-09-28
申请号：PH32289
申请日：1985-05-17
Applicant: IBM
Inventor： RACKLEY DARWIN PRESTON , YOSIM PAUL STEWART , SAENZ JESUS ANDRES
Abstract: A digital display system includes a monitor arranged to receive digital display data and synchronising signals to develop displays on a cathode ray tube. The monitor is switched between different line structure and/or colour definition modes in response to the polarity of one of the vertical or horizontal synchronising signals trains. A circuit receives this train to provide control signals to the horizontal time base and/or a colour signal code converter. The time base control signal, in accordance with its binary value, controls the frequency of the time base. The colour converter, in response to the control signals, either passes colour signals received in parallel over six input lines without change to the cathode ray tube drive circuits or converts colour signals on four of the input lines to output signals on the six lines to the drive circuits.
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Patent Agency Ranking
公开(公告)号：DE3584403D1
公开(公告)日：1991-11-21
申请号：DE3584403
申请日：1985-06-05
Applicant: IBM
Inventor： RACKLEY DARWIN PRESTON , SAENZ JESUS ANDRES , YOSIM PAUL STEWART
Abstract: A digital display system includes a monitor arranged to receive digital display data and synchronising signals to develop displays on a cathode ray tube. The monitor is switched between different line structure and/or colour definition modes in response to the polarity of one of the vertical or horizontal synchronising signals trains. A circuit receives this train to provide control signals to the horizontal time base and/or a colour signal code converter. The time base control signal, in accordance with its binary value, controls the frequency of the time base. The colour converter, in response to the control signals, either passes colour signals received in parallel over six input lines without change to the cathode ray tube drive circuits or converts colour signals on four of the input lines to output signals on the six lines to the drive circuits.
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公开(公告)号：DE3483301D1
公开(公告)日：1990-10-31
申请号：DE3483301
申请日：1984-07-05
Applicant: IBM
Inventor： KUMMER DAVID ALLEN , RACKLEY DARWIN PRESTON , SAENZ JESUS ANDRES
Abstract: @ A raster scan display system includes a plurality of storage maps (MAPO to MAP4). These maps are addressable in either of two modes. In the first mode each map contains bit mapped data and the maps are addressed together to provide colour signals from which colour video signals are derived. In the second mode, one map contains character representing data and a further map, character display dot patterns. In this mode the first map is addressed to provide partial addresses for the further map. These partial addresses are combined with row scan data signals to access the further map from which the character display dot data is used to generate the video signals.
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公开(公告)号：MX157249A
公开(公告)日：1988-11-08
申请号：MX20231684
申请日：1984-08-09
Applicant: IBM
Inventor： KUMMER DAVID ALLEN , SAENZ JESUS ANDRES , TRYNOSKY STEPHEN WAYNE
Abstract: In a raster scan digital display system, a display image is stored, as coded characters or a bit map, which is larger than the display image. In order to define an image, within the stored image, for display, the addressing system for the memory (or memories) storing the image include a display image defining circuit. This circuit includes an address counter which is incremented to define successive addresses of data in a line of the displayed image, or row of characters therein. The circuit includes a first register to receive the initial address of a display image and a second register to receive a value indicating the width of the stored image. For the initial line (or character row) of a displayed image, the address counter is loaded from the first register and incremented from the initial address. For each subsequent line (or character row) the address from which the counter is incremented is the sum of the initial address of the previous line (or character row) and the value in the second register.
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公开(公告)号：DE3278982D1
公开(公告)日：1988-10-06
申请号：DE3278982
申请日：1982-06-29
Applicant: IBM
Inventor： DEAN MARK EDWARD , KUMMER DAVID ALLEN , SAENZ JESUS ANDRES
Abstract: A 3.58 MHz subcarrier signal and a 14.318 MHz clock signal are applied to three flipflops (50, 52 and 54) in such a manner that there appears on the output terminals (Q and Q) of the latches individual phase-shifted subcarriers having relative phases of 0°, 180°, 90°, 270°, 135° and 315°, respectively, representing the colors yellow, blue, red, cyan, magenta and green, respectively. Computer-generated digital color signals (+BLUE, +GREEN, +RED) are applied to the switching inputs (A, B, C) of a multiplexer (56) in order selectively to switch to the output of the multiplexer individual ones of the phase-shifted subcarriers in accordance with the code represented by the digital color signals. The individual subcarriers are combined in a summing circuit (62, 64) with television synchronizing and blanking pulses to produce a composite video color signal which is directly compatible with a conventional composite monitor and, after R.F. modulation, with a conventional television receiver. Brighter versions of the colors are obtained by increasing the direct current level (+INTENSITY) at the summing circuit.
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公开(公告)号：AT68621T
公开(公告)日：1991-11-15
申请号：AT85106931
申请日：1985-06-05
Applicant: IBM
Inventor： RACKLEY DARWIN PRESTON , SAENZ JESUS ANDRES , YOSIM PAUL STEWART
Abstract: A digital display system includes a monitor arranged to receive digital display data and synchronising signals to develop displays on a cathode ray tube. The monitor is switched between different line structure and/or colour definition modes in response to the polarity of one of the vertical or horizontal synchronising signals trains. A circuit receives this train to provide control signals to the horizontal time base and/or a colour signal code converter. The time base control signal, in accordance with its binary value, controls the frequency of the time base. The colour converter, in response to the control signals, either passes colour signals received in parallel over six input lines without change to the cathode ray tube drive circuits or converts colour signals on four of the input lines to output signals on the six lines to the drive circuits.
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