公开(公告)号：DE69823601D1

公开(公告)日：2004-06-09

申请号：DE69823601

申请日：1998-08-24

Applicant: IBM

Inventor： KIRIHATA TOSHIAKI

IPC: G11C11/401 ,  G11C7/10 ,  G11C7/18 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4096 ,  G11C7/00

Abstract: A multi-bank DRAM has a hierarchical column select line architecture. The DRAM is provided with a plurality of memory cells which are organised in at least two banks. Each of the banks includes memory cells which are arranged in rows and columns. The memory cells store data provided by at least one bit line and at least one data line. The DRAM includes: a first switch for selecting one of the two banks; and a second switch connected to the first switch for selecting one of the columns, wherein the first and second switches couple one of the bit lines to one of the data lines, enabling data to be written into or read out of memory cells common to the selected bank and to the selected column. The first switch is controlled by a plurality of bank CSLs (BCSLs), wherein the BCSLs are shared by some of the blocks within the same bank, but not by any of the blocks in other banks. The second switch is controlled by a plurality of global CSLs (GCSLs), the GCSLs being shared by all remaining banks within a unit. The BCSLs and GCSLs are controlled by the bank column decoder and by the global column decoder.

公开(公告)号：SG67484A1

公开(公告)日：1999-09-21

申请号：SG1998000502

申请日：1998-03-06

Applicant: IBM

Inventor： KIRIHATA TOSHIAKI

IPC: G11C29/04 ,  G11C29/00 ,  G11C7/00

Abstract: A method of making a memory fault-tolerant through the use of a variable size redundancy replacement (VSRR) circuit arrangement. A redundancy array supporting the primary arrays forming the memory includes a plurality of variable size redundancy units, each of which encompassing a plurality of redundant elements. The redundant units used for repairing faults in the memory are independently controlled. All the redundancy elements within a repair unit are preferably replaced simultaneously. The redundancy elements in the redundancy unit are controlled by decoding address lines. The variable size that characterizes this configuration makes it possible to choose the most effective redundancy unit, and in particular, the one most closely fitting the size of the cluster of failures to be replaced. This method significantly reduces the overhead created by added redundancy elements and control circuitry, while improving the access speed and reducing power consumption. Finally, a fault-tolerant block redundancy controlled by a priority decoder makes it possible to use VSRR units for repairing faults in the block redundancy prior to its use for replacing a defective block within the memory.

公开(公告)号：DE102013224104A1

公开(公告)日：2014-06-12

申请号：DE102013224104

申请日：2013-11-26

Applicant: IBM

Inventor： CHELLAPPA SRIVATSAN ,  IYER SUBRAMANIAN S ,  KIRIHATA TOSHIAKI ,  ROSENBLATT SAMI

IPC: G06F21/44

Abstract: Ausführungsformen der vorliegenden Erfindung stellen einen Echtheitsnachweisdienst eines Chips bereit, der eine chipspezifische Kennung (ID) aufweist. Gemäß einer typischen Ausführungsform wird eine Echtheitsnachweiseinheit bereitgestellt, die ein Erkennungs-(ID-)Modul, ein Selbsttest-Modul und eine chipspezifische Komponente enthält. Die chipspezifische Komponente ist einem Chip zugehörig und enthält ein chipspezifisches Merkmal. Das Selbsttest-Modul ruft das chipspezifische Merkmal ab und übermittelt dieses an das Erkennungs-Modul. Das Erkennungs-Modul empfängt das chipspezifische Merkmal, erzeugt unter Verwendung des chipspezifischen Merkmals einen ersten Echtheitsnachweiswert und speichert den Echtheitsnachweiswert in einem Speicher. Das Selbsttest-Modul erzeugt unter Verwendung einer Echtheitsnachweisabfrage einen zweiten Echtheitsnachweiswert. Das Erkennungs-Modul enthält eine Vergleichsschaltung, die den ersten Echtheitsnachweiswert mit dem zweiten Echtheitsnachweiswert vergleicht und auf der Grundlage der Ergebnisse des Vergleichs der beiden Werte miteinander einen Echtheitsnachweis-Ausgabewert erzeugt.

公开(公告)号：CA2852883A1

公开(公告)日：2013-05-30

申请号：CA2852883

申请日：2012-09-13

Applicant: IBM

Inventor： FAINSTEIN DANIEL J ,  CESTERO ALBERTO ,  IYER SUBRAMANIAN S ,  KIRIHATA TOSHIAKI ,  ROSENBLATT SAMI ,  ROBSON NORMAN W

IPC: G11C29/00 ,  G06F21/00

Abstract: A random intrinsic chip ID generation employs a retention fail signature. A 1st and 2nd ID are generated using testing settings with a 1st setting more restrictive than the 2nd, creating more fails in the 1st ID bit string 275 that includes 2nd ID bit string 290. A retention pause time controls the number of retention fails, adjusted by a BIST engine 625, wherein the fail numbers 803, 920 satisfy a predetermined fail target. Verification confirms whether the 1st ID includes the 2nd ID bit string, the ID being the one used for authentication. Authentication is enabled by a 3rd ID with intermediate condition such that 1st ID includes 3rd ID bit string and 3rd ID includes 2nd ID bit string. The intermediate condition includes a guard-band to eliminate bit instability problem near the 1st and 2nd ID boundary. The intermediate condition is changed at each ID read operation, resulting in a more secure identification.

公开(公告)号：DE69833093D1

公开(公告)日：2006-03-30

申请号：DE69833093

申请日：1998-09-04

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  WONG HING ,  KRSNKI BOZIDAR

IPC: G01R31/28 ,  G11C29/00 ,  G11C11/401 ,  G11C29/04 ,  G11C29/50 ,  G11C29/56

Abstract: The method involves generating a dummy timing cycle for disabling bitline equalizer by supplying a negative test pulse. The bitline equaliser is disabled to set up a floating bitline test mode. A row address strobe signal is enabled and read operation is started in a normal mode. Defective bitlines are detected during dummy timing cycles.

公开(公告)号：DE60110297D1

公开(公告)日：2005-06-02

申请号：DE60110297

申请日：2001-02-23

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  DANIEL GABRIEL

IPC: G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G06F11/20

Abstract: A memory device that includes a plurality of data storage cells; at least one redundancy data storage cell; a redundancy match detection circuit; and a means for coupling programmable fuses to the redundancy match detection circuit, wherein a defective data storage is replaced by one redundancy data storage when the redundancy match detection detects a pre-determined condition set by said programmable fuse is described. Decoding is accomplished by a data bus selecting the e-fuse to be blown. The data bus is also used for reading the state of the e-fuses to ensure that the e-fuses are correctly blown. Power is effectively applied to the selected e-fuses while sharing the data bus for e-fuse decoding and verification. In order to reduce the number of communication channels between e-fuses and the redundancy match detection circuitry, the transfer operation uses time multiplexing, allowing e-fuse information to be transferred to the redundancy match detection circuitry sequentially. The actual time multiplexing operation for performing the transfer is preferably enabled only after the chip power-up state.

公开(公告)号：DE69906406T2

公开(公告)日：2004-01-08

申请号：DE69906406

申请日：1999-01-29

Applicant: IBM ,  SIEMENS AG

Inventor： KIRIHATA TOSHIAKI ,  PFEFFERL KARL-PETER

IPC: G11C29/04 ,  G11C29/00 ,  G06F11/20

Abstract: A method and apparatus for repairing a memory device through a selective domain redundancy replacement (SDRR) arrangement, following the manufacture and test of the memory device. A redundancy array supporting the primary arrays forming the memory includes a plurality of redundancy groups, at least one of which contains two redundancy units. A redundancy replacement is hierarchically realized by a domain that includes a faulty element within the redundancy group, and by a redundancy unit that repairs the fault within the selected domain. SDRR allows a domain to customize the optimum number and size redundancy units according to existing fault distributions, while achieving a substantially saving in real estate, particularly over the conventional flexible redundancy replacement, in term of the number of fuses (10-20%). By combining several types of redundancy groups, each having a different number of redundancy elements, full flexible redundancy replacement can also be achieved. Consequently, this approach compensates for the drawback of existing intra-block replacements, flexible redundancy replacements, and variable domain redundancy replacements, while improving repairability irrespective of the fault distribution within the memory device.

公开(公告)号：DE10315050A1

公开(公告)日：2003-11-27

申请号：DE10315050

申请日：2003-04-02

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  MUELLER GERHARD ,  HANSON DAVID

IPC: H03K19/0185 ,  H03L5/00

Abstract: A low voltage level shifter circuit with an embedded latch, implemented on a signal line having thereon low voltage signals. There is included a low voltage level shifter circuit configured to receive a low voltage input signal from a first portion of the signal line and output a higher voltage output signal on a second portion of the signal line. A latching circuit is also included, and is configured to latch the low voltage input signal from the first portion of the signal line.

公开(公告)号：DE69811421T2

公开(公告)日：2003-10-23

申请号：DE69811421

申请日：1998-03-23

Applicant: IBM

Inventor： KIRIHATA TOSHIAKI

IPC: G11C29/00 ,  G06F11/20

Abstract: A redundancy replacement (VSRR) arrangement or method for making a memory fault-tolerant employs a plurality of variable size redundancy units (RUo - RU15), each of which encompasses a plurality of redundancy elements (RE). The redundancy units, used for repairing faults in the memory, are independently controlled. All the redundancy elements within a repair unit are preferably replaced simultaneously. The redundancy elements in the redundancy unit are controlled by decoding address lines. The variable size that characterizes this configuration makes it possible to choose the most effective redundancy unit, and in particular, the one most closely fitting the size of the cluster of failures to be replaced. This configuration significantly reduces the overhead created by added redundancy elements and control circuitry, while improving the access speed and reducing power consumption. Finally, a fault-tolerant block redundancy controlled by a priority decoder makes it possible to use VSRR units for repairing faults in the block redundancy prior to its use for replacing a defective block within the memory.

公开(公告)号：DE10314615A1

公开(公告)日：2003-10-23

申请号：DE10314615

申请日：2003-04-01

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  MUELLER GERHARD

IPC: H03F3/04 ,  H03K19/0175 ,  H03K19/094

Abstract: A repeater circuit having improved switching speed and reduced power consumption is described. The repeater circuit is configured to receive an input signal from a first segment of a signal line and pass the signal to a second segment of the signal line in response to an active control signal.