公开(公告)号：JP2006163596A

公开(公告)日：2006-06-22

申请号：JP2004351492

申请日：2004-12-03

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： SUGANUMA TOSHIO ,  KOMATSU HIDEAKI

IPC: G06F12/00

CPC classification number: G06F17/30377 ,  Y10S707/99938

Abstract: PROBLEM TO BE SOLVED: To accelerate transaction processing to a data base from before.
SOLUTION: The information processing system which performs the transaction processing to the data base includes a processing program acquiring section for acquiring a processing program which is program transaction processing to the data base being described to be, an object data selecting section which selects at least one object data used as an object accessed by transaction processing of the transaction program of the data base, and a rewriting processing insertion section which inserts object data rewriting processing which rejects the object data updated by the transaction processing among the object data to the data base into the section performed after the accessing object data finally before committing processing result in the processing program.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：从之前加速到数据库的事务处理。 解决方案：对数据库执行事务处理的信息处理系统包括：处理程序获取部分，用于获取对被描述为数据库的程序事务处理的处理程序，对象数据选择部分选择 用作通过数据库的交易程序的事务处理访问的对象的至少一个对象数据，以及重写处理插入部，其将对象数据重写处理插入到对象数据中，所述对象数据重写处理将对象数据中的由事务处理更新的对象数据拒绝到 数据库进入到处理程序结束之后访问对象数据之后执行的部分。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2006127302A

公开(公告)日：2006-05-18

申请号：JP2004316996

申请日：2004-10-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： NAKAIKE TAKUYA ,  KOMATSU HIDEAKI ,  KONO SEIICHI

IPC: G06F9/45

CPC classification number: G06F1/3203 ,  G06F8/4432 ,  G06F9/4893 ,  Y02D10/24 ,  Y02D10/41

Abstract: PROBLEM TO BE SOLVED: To reduce energy consumption accompanying the execution of a program by adjusting the computing capacity of a central processing unit more accurately than before. SOLUTION: An information processor for setting appropriate computing capacity to the central processing unit capable of changing the computing capacity during execution comprises: an execution time measurement part for changing the computing capacity of the central processing unit and measuring execution time each time a program area is executed during the execution of an execution program for each of the plurality of program areas included in the execution program; an appropriate computing capacity judgement part for judging the appropriate computing capacity with which the program area is to be executed by the central processing unit on the basis of the execution time for each computing capacity measured for the respective program areas; and a computing capacity setting part for performing setting for executing the program area by the appropriate computing capacity of the program area when the program area is executed again during the execution of the execution program for the respective program areas. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：通过比以前更精确地调整中央处理单元的计算能力，减少伴随程序执行的能量消耗。 解决方案：用于向中央处理单元设置能够在执行期间改变计算能力的适当计算能力的信息处理器包括：执行时间测量部分，用于改变中央处理单元的计算能力，并且每次测量执行时间 在对执行程序中包括的多个程序区域中的每一个执行执行程序期间执行程序区域; 基于针对各个程序区域测量的每个计算能力的执行时间，判断中央处理单元执行程序区域的适当计算能力的适当计算能力判断部分; 以及计算能力设定部件，用于当在执行相应程序区域的执行程序期间再次执行程序区域时，执行程序区域的适当计算能力执行程序区域的设置。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2005215884A

公开(公告)日：2005-08-11

申请号：JP2004020213

申请日：2004-01-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： OGATA KAZUNORI ,  ONODERA TAMIYA ,  KOMATSU HIDEAKI

IPC: G06F11/28 ,  G06F9/45

CPC classification number: G06F11/3612 ,  G06F9/45516 ,  G06F11/3636

Abstract: PROBLEM TO BE SOLVED: To facilitate the debugging of a dynamic compiler by reproducing the same execution instruction sequence as an execution instruction sequence generated by the dynamic compiler. SOLUTION: A compiler program allows a computer to function in the following ways: an execution state acquisition section acquires the execution state of a program; a dynamic compiling section generates a different execution sequence in accordance with the execution state by compiling part of a program to be executed based on the execution state in the course of executing the program; an execution state recording section records the execution state on a storage region allocated to the memory of the computer; a file reading section reads a file including the contents of the storage region allocated to the memory saved on a storage device by the computer from the storage device; and a reproducible compiling section generates the same execution instruction sequence as the execution instruction sequence generated by the dynamic compiling section in the course of executing the program by compiling part of the program based on the execution state acquired from the file. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：通过再现与动态编译器生成的执行指令序列相同的执行指令序列来促进动态编译器的调试。 解决方案：编译程序允许计算机以下列方式运行：执行状态获取部分获取程序的执行状态; 动态编译部分根据执行状态通过在执行程序的过程中基于执行状态编译要执行的程序的一部分来生成不同的执行序列; 执行状态记录部分将执行状态记录在分配给计算机的存储器的存储区域上; 文件读取部从存储装置读取包含由计算机分配给保存在存储装置上的存储器的存储区域的内容的文件; 并且可重现的编译部分根据从文件获取的执行状态编译程序的一部分，在执行程序的过程中产生与动态编译部分生成的执行指令序列相同的执行指令序列。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004355279A

公开(公告)日：2004-12-16

申请号：JP2003151478

申请日：2003-05-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： INAGAKI TATSUSHI ,  ONODERA TAMIYA ,  KOMATSU HIDEAKI

IPC: G06F9/45

Abstract: PROBLEM TO BE SOLVED: To enable a code conversion device 10 for converting a code to be converted such as a Java byte code into a machine language code to generate the machine language code associated with effective prefetch. SOLUTION: Under the consideration of a pointer reference load instruction in each iteration of a loop on a program and a data dependent load instruction with respect to the pointer reference load instruction in each iteration, first and second detecting means 17 and 18 check inter-iteration and in-iteration strides associated with the pointer reference load instruction and the data dependent load instruction by performing access to a heap memory 19. First and second machine language code part generating means generate a predetermined machine language code part on the basis of the inter-iteration and in-iteration constant strides set by a setting means 22. As a result, in machine language code execution, data associated with the data dependent load instruction are effectively prefetched from a heap memory 13 to a cache memory. COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JP2002259135A

公开(公告)日：2002-09-13

申请号：JP2001055996

申请日：2001-02-28

Applicant: IBM

Inventor： KAWAHITO MOTOHIRO ,  KOMATSU HIDEAKI ,  JOHN FARLEY

IPC: G06F9/45 ,  G06F9/44

Abstract: PROBLEM TO BE SOLVED: To shorten time required for compilation including optimization based on specification and to suppress memory consumption for compilation. SOLUTION: The compiler 10 is provided with an influence degree analysis part 12 for analyzing how much the execution speed of a program to be compiled can be improved by fixing the parameter of a prescribed instruction in the program to a specific state, a specification data selection part 13 for taking the statistics of appearance frequency in each state of the parameter of the instruction analyzed by the analysis part 12 and determining which state is to be adopted for the parameter of the instruction based on the obtained static information and a specified compiling processing part 14 for generating a specified pass fixing the parameter of the prescribed instruction to the specific state in the program based on the processing results of the analysis part 12 and the selection part 13.

公开(公告)号：JP2001075814A

公开(公告)日：2001-03-23

申请号：JP23253399

申请日：1999-08-19

Applicant: IBM

Inventor： KOSEKI SATOSHI ,  INAGAKI TATSUSHI ,  YASUE TOSHIAKI ,  KOMATSU HIDEAKI ,  TAKEUCHI MIKIO

IPC: G06F9/45

Abstract: PROBLEM TO BE SOLVED: To effectively optimize an object code in the range satisfying limitation caused by the number of physical registers of a processor. SOLUTION: This compiler device performs code generation from a program represented by a DAG(directed acyclic graph) while evaluating the number of used registers and the number of execution cycles and optimizes a code to be generated. That is, the compiler calculates the number of cycles with which each operation can be executed on the DAG and the number of the currently available registers, performs code generation while preceding an operator on an execution path that takes the most time in the DAG in a part where the number of registers is sufficient, and performs code generation while preceding such an operator as to reduce the number of used registers when the number of registers is not sufficient.

公开(公告)号：JP2000207221A

公开(公告)日：2000-07-28

申请号：JP71299

申请日：1999-01-05

Applicant: IBM

Inventor： KAWAHITO MOTOHIRO ,  KOMATSU HIDEAKI ,  YASUE TOSHIAKI

IPC: G06F9/45 ,  G06F9/44

Abstract: PROBLEM TO BE SOLVED: To decrease the frequency of an array range check and to increase execution speed by generating a code for an array range check included in array range checks. SOLUTION: Array range checks, corresponding to array access operations, are integrated under specific conditions and the result is stored in a storage device (110). An array range check is assigned to one ore more flags (120). Codes to be stored in the assigned flags are generated and stored in a storage device (130). If versioning is carried out (140), a versioning header is generated by using the flags, and a version of flag check success and a version of flag check failure are generated and stored in the storage device (150). A code, which invalidates a code is generated and stored in the storage device (160). Consequently, array range checks which are to be removed becomes few.

公开(公告)号：JP2000020320A

公开(公告)日：2000-01-21

申请号：JP17094598

申请日：1998-06-18

Applicant: IBM

Inventor： OGASAWARA TAKESHI ,  KOMATSU HIDEAKI

IPC: G06F9/45 ,  G06F9/48 ,  G06F9/46

Abstract: PROBLEM TO BE SOLVED: To enable a just-in-time compiler to execute optimizing processing of exchanging instruction execution order while guaranteeing an exact exception. SOLUTION: When the instruction order of S1, S2, E1, S3 and S4 is exchanged as shown in the figure, for example, the part from forward moved instruction E1 to instruction S2 located before E1 is registered as an interruption inhibition section R1 and the part from forward moved instruction S4 to instruction S3 located before S4 is registered as an interruption inhibition section R2 (S is an instruction having operation observable from the outside at the time of the execution and E is an instruction having the possibility of the exception occurrence.). The instruction S4 following E1 in the original order is registered as an invalid instruction at the time the exception occurs in R1. When the exception occurs in E1, an interruption handler is started, the instruction in the interruption inhibition section R1 is copied to the other area and S4 is not copied. Further, the branch code to an exception processing routine is added to the end of the copy and the execution is restarted from S1.

公开(公告)号：JPH11338699A

公开(公告)日：1999-12-10

申请号：JP12702498

申请日：1998-05-11

Applicant: IBM

Inventor： YASUE TOSHIAKI ,  KOMATSU HIDEAKI ,  OGASAWARA TAKESHI

IPC: G06F9/45 ,  G06F9/42 ,  G06F9/44

Abstract: PROBLEM TO BE SOLVED: To increase the application range of execution optimization due to method inlining in a language having a security function. SOLUTION: A 1st method with self-recursion includes a step where a code needed for looping by tail recursion is produced, and a step where a code for counting the repetition number of a loop is produced. A security manager corrects depth in a storage area of a frame that is related to a 2nd method. Also, it includes a step where the code of the 1st method undergoes inlining in the 2nd method that includes the 1st method access in which processing is undetermined after being accessed, and a step where access relation of the 1st and 2nd methods in a state before making inlining the 1st method code is acquired and later is stored in an available storage area.

公开(公告)号：JPH1040223A

公开(公告)日：1998-02-13

申请号：JP15583196

申请日：1996-06-17

Applicant: IBM

Inventor： OGASAWARA TAKESHI ,  KOMATSU HIDEAKI

IPC: G06F15/16 ,  G06F9/45 ,  G06F15/163

Abstract: PROBLEM TO BE SOLVED: To fast recognize the set communication for the uniform problems in an execution mode by calculating a communication set in each dimension of an array based on the data structure and the processor expression and then extracting the set communication from the communication set of each dimension when the communication is performed. SOLUTION: An ITR list consists of an ITR block and an ITR master, i.e., a management data structure. The ITR block includes an array section that is designated by three sets of start, end and jump width and four sets which designate the opposite party of communication of the relevant area. Then the communication set of the ITR block is calculated in each dimension based on the management data structure of the ITR master and the processor expression that is not affected by the number of processors, and the set communication is extracted from the communication set of each dimension when the communication is performed. Thus, the set communication is fast recognized in an execution mode against the uniform problems.