公开(公告)号：MX338375B

公开(公告)日：2016-04-13

申请号：MX2014015290

申请日：2012-11-22

Applicant: IBM

Inventor： GREINER DAN ,  SLEGEL TIMOTHY ,  MITRAN MARCEL ,  JACOBI CHRISTIAN

IPC: G06F11/07

Abstract: Cuando se presenta el aborto de una transacción en un sistema de computadora, se toma una determinación en cuanto a si la información de diagnóstico va a ser almacenada en uno más bloquees de diagnóstico de transacción (TDB). Hay diferentes tipos de bloques de diagnóstico de transacción para aceptar información de diagnóstico de transacción para aceptar información de diagnóstico dependiendo del tipo de aborto y otras consideraciones. Como ejemplos, hay un TDB especifico del programa en el cual la información es almacenada si se provee una dirección de TDB válida en una instrucción de comienzo de transacción; un TDB de interrupción del programa que es almacenado cuando el programa es abortado debido a una interrupción y un TDB de intercepción del programa, que es almacenado cuando un aborto da como resultado una intercepción.

公开(公告)号：ZA201400730B

公开(公告)日：2015-10-28

申请号：ZA201400730

申请日：2014-01-30

Applicant: IBM

Inventor： COPELAND REID ,  GAINEY JR CHARLES ,  SCHWARZ ERIC MARK ,  MITRAN MARCEL ,  SLEGEL TIMOTHY ,  CARLOUGH STEVEN

Abstract: Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location.

公开(公告)号：CA2831711A1

公开(公告)日：2015-04-30

申请号：CA2831711

申请日：2013-10-31

Applicant: IBM CANADA

Inventor： MITRAN MARCEL ,  VOKHSHOORI VISDA

IPC: G06F8/41 ,  G06F9/30

Abstract: An illustrative embodiment of a computer-implemented method for safe conditional operation when storage access cannot be proven safe, receives a portion of source code for a transaction by an enhanced compiler and analyzes the portion of source code received, by the enhanced compiler to determine whether the portion of source code analyzed by the enhanced compiler is a candidate for transformation. Responsive to a determination the portion of source code analyzed by the enhanced compiler is a candidate for transformation, the portion of source code analyzed is transformed to use a conditional operation in a first portion of transformed code, wherein a respective conditional operation uses hardware transaction memory to invoke retry operations within hardware and a branch is added, directed to an original code portion, in a second portion of transformed code, wherein code of the branch is a recovery portion containing the original code portion.

公开(公告)号：MX2014015290A

公开(公告)日：2015-04-10

申请号：MX2014015290

申请日：2012-11-22

Applicant: IBM

Inventor： GREINER DAN ,  SLEGEL TIMOTHY ,  MITRAN MARCEL ,  JACOBI CHRISTIAN

IPC: G06F11/07

Abstract: Cuando se presenta el aborto de una transacción en un sistema de computadora, se toma una determinación en cuanto a si la información de diagnóstico va a ser almacenada en uno más bloquees de diagnóstico de transacción (TDB). Hay diferentes tipos de bloques de diagnóstico de transacción para aceptar información de diagnóstico de transacción para aceptar información de diagnóstico dependiendo del tipo de aborto y otras consideraciones. Como ejemplos, hay un TDB especifico del programa en el cual la información es almacenada si se provee una dirección de TDB válida en una instrucción de comienzo de transacción; un TDB de interrupción del programa que es almacenado cuando el programa es abortado debido a una interrupción y un TDB de intercepción del programa, que es almacenado cuando un aborto da como resultado una intercepción.

公开(公告)号：GB2517876A

公开(公告)日：2015-03-04

申请号：GB201500043

申请日：2013-05-20

Applicant: IBM

Inventor： PRASKY BRIAN ROBERT ,  VASILEVSKIY ALEXANDER ,  BONANNO JAMES JOSEPH ,  SIU JORAN ,  MITRAN MARCEL ,  SLEGEL TIMOTHY

IPC: G06F9/38 ,  G06F9/30

Abstract: Embodiments relate to branch prediction preloading. An aspect includes a system for branch prediction preloading. The system includes an instruction cache and branch target buffer (BTB) coupled to a processing circuit, the processing circuit configured to perform a method. The method includes fetching a plurality of instructions in an instruction stream from the instruction cache, and decoding a branch prediction preload instruction in the instruction stream. An address of a predicted branch instruction is determined based on the branch prediction preload instruction. A predicted target address is determined based on the branch prediction preload instruction. A mask field is identified in the branch prediction preload instruction, and a branch instruction length is determined based on the mask field. Based on executing the branch prediction preload instruction, the BTB is preloaded with the address of the predicted branch instruction, the branch instruction length, the branch type, and the predicted target address.

公开(公告)号：GB2512799A

公开(公告)日：2014-10-08

申请号：GB201414237

申请日：2013-05-21

Applicant: IBM

Inventor： GREINER DAN ,  JACOBI CHRISTIAN ,  SLEGEL TIMOTHY ,  MITRAN MARCEL

IPC: G06F9/30 ,  G06F9/52

Abstract: A TRANSACTION BEGIN instruction and a TRANSACTION END instruction are provided. The TRANSACTION BEGIN instruction causes either a constrained or nonconstrained transaction to be initiated, depending on a field of the instruction. The TRANSACTION END instruction ends the transaction started by the TRANSACTION BEGIN instruction.

公开(公告)号：SG11201404861QA

公开(公告)日：2014-09-26

申请号：SG11201404861Q

申请日：2013-03-01

Applicant: IBM

Inventor： FARRELL MARK S ,  GAINEY JR CHARLES W ,  MITRAN MARCEL ,  SHUM CHUNG-LUNG KEVIN ,  SLEGEL TIMOTHY J ,  SMITH BRIAN LEONARD ,  STOODLEY KEVIN A

IPC: G06F11/34

Abstract: Aspects relate to enabling and disabling execution of a run-time instrumentation facility. An instruction for execution by the processor in a lesser privileged state is fetched by the processor. It is determined, by the processor, that the run-time instrumentation facility permits execution of the instruction in the lesser-privileged state and that controls associated with the run-time instrumentation facility are valid. The run-time instrumentation facility is disabled based on the instruction being a run-time instrumentation facility off (RIOFF) instruction. The disabling includes updating a bit in a program status word (PSW) of the processor to indicate that run-time instrumentation data should not be captured by the processor. The run-time instrumentation facility is enabled based on the instruction being a run-time instrumentation facility on (RION) instruction. The enabling includes updating the bit in the PSW to indicate that run-time instrumentation data should be captured by the processor.

公开(公告)号：SG11201404860VA

公开(公告)日：2014-09-26

申请号：SG11201404860V

申请日：2013-03-01

Applicant: IBM

Inventor： GAINEY JR CHARLES W ,  MITRAN MARCEL ,  SHUM CHUNG-LUNG KEVIN ,  STOODLEY KEVIN A

IPC: G06F11/34

公开(公告)号：AU2013233831A1

公开(公告)日：2014-09-11

申请号：AU2013233831

申请日：2013-03-01

Applicant: IBM

Inventor： GAINEY JR CHARLES W ,  MITRAN MARCEL ,  SHUM CHUNG-LUNG KEVIN ,  STOODLEY KEVIN A

IPC: G06F11/34

Abstract: Embodiments of the invention relate to implementing run-time instrumentation directed sampling. An aspect of the invention includes a method for implementing run-time instrumentation directed sampling. The method includes fetching a run-time instrumentation next (RINEXT) instruction from an instruction stream. The instruction stream includes the RINEXT instruction followed by a next sequential instruction (NSI) in program order. The method further includes executing the RINEXT instruction by a processor. The executing includes determining whether a current run-time instrumentation state enables setting a sample point for reporting run-time instrumentation information during program execution. Based on the current run-time instrumentation state enabling setting the sample point, the NSI is a sample instruction for causing a run-time instrumentation event. Based on executing the NSI sample instruction, the run-time instrumentation event causes recording of run-time instrumentation information into a run-time instrumentation program buffer as a reporting group.

公开(公告)号：CA2852862A1

公开(公告)日：2013-07-04

申请号：CA2852862

申请日：2012-11-13

Applicant: IBM

Inventor： CARLOUGH STEVEN ,  SCHWARZ ERIC MARK ,  SLEGEL TIMOTHY ,  GAINEY CHARLES JR ,  MITRAN MARCEL ,  COPELAND REID

IPC: G06F9/30 ,  G06F9/318

Abstract: Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location.