公开(公告)号：GB2472166B

公开(公告)日：2011-05-18

申请号：GB201018230

申请日：2006-10-24

Applicant: INTEL CORP

Inventor： BASKARAN RAJASHREE ,  RAMANATHAN SHRIRAM ,  MORROW PATRICK

IPC: H01L23/367 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065

公开(公告)号：GB2472166A

公开(公告)日：2011-01-26

申请号：GB201018230

申请日：2006-10-24

Applicant: INTEL CORP

Inventor： BASKARAN RAJASHREE ,  RAMANATHAN SHRIRAM ,  MORROW PATRICK

IPC: H01L23/367 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065

Abstract: A method is disclosed relating to stacked wafer or die packaging with enhanced thermal and device performance, the method comprises providing a heat spreading and stress engineering layer 260 on a substrate surface 210, the substrate surface 210 being opposite a metallisation region 230 which, in turn, rests on a device layer 220 of the substrate; the metal layer 250 is then exposed by providing a via opening through the heat spreading and stress engineering layer 260, the substrate 210 and the device layer 220; a sidewall insulator 290 is provided on the side walls of the via opening and then the via opening is filled with a conductive material 295. Also disclosed is a method where a trench is formed in a substrate surface opposite a metallisation layer, the metallisation layer being formed on a device layer formed in the substrate; forming an insulating layer over the surface and trench; exposing the metallisation layer by forming a via through the insulating layer, the substrate and the device layer; forming a second insulating layer in the first insulating layer and via; exposing the metallisation layer again; selectively filling the trench and via opening with conductive material; such that the conductive material forms a conductive via and a heat spreading and stress engineering region.

公开(公告)号：GB2444467B

公开(公告)日：2010-12-08

申请号：GB0806342

申请日：2006-10-24

Applicant: INTEL CORP

Inventor： BASKARAN RAJASHREE ,  RAMANATHAN SHRIRAM ,  MORROW PATRICK

IPC: H01L23/367 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065

Abstract: An apparatus includes a metallization region including a plurality of metal layers on a device layer of a substrate, a via extending through the substrate and the device layer, and a heat spreading and stress engineering region in the substrate and adjacent to the device layer. The via contacts a metal layer in the metallization region.

公开(公告)号：DE112006002909T5

公开(公告)日：2008-09-18

申请号：DE112006002909

申请日：2006-10-24

Applicant: INTEL CORP

Inventor： BASKARAN RAJASHREE ,  RAMANATHAN SHRIRAM ,  MORROW PATRICK

IPC: H01L23/367 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065

Abstract: An apparatus includes a metallization region including a plurality of metal layers on a device layer of a substrate, a via extending through the substrate and the device layer, and a heat spreading and stress engineering region in the substrate and adjacent to the device layer. The via contacts a metal layer in the metallization region.

公开(公告)号：GB2444467A

公开(公告)日：2008-06-04

申请号：GB0806342

申请日：2006-10-24

Applicant: INTEL CORP

Inventor： BASKARAN RAJASHREE ,  RAMANATHAN SHRIRAM ,  MORROW PATRICK

IPC: H01L23/367 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065

Abstract: A substrate has a device layer (210, 310) and metallization region (230, 315) Within the substrate are provided electrically conductive through vias (270, 350) and thermally conductive regions (260, 365). The thermally conductive regions may be formed by deposition into a trench, or by patterning. The substrate may be provided in a stacked arrangement.

公开(公告)号：DE60036410D1

公开(公告)日：2007-10-25

申请号：DE60036410

申请日：2000-11-27

Applicant: INTEL CORP

Inventor： MURTHY ANAND S ,  CHAU ROBERT S ,  MORROW PATRICK ,  MCFADDEN ROBERT S

IPC: H01L29/06 ,  H01L21/3065 ,  H01L21/336

Abstract: A microelectronic structure includes at least one source/drain terminal of a first conductivity type that is partially isolated from a region of semiconductor material of a second conductivity type. In a further aspect of the invention, a process for forming a microelectronic structure, such as a MOSFET, having at least one source/drain terminal of a first conductivity type that is partially isolated from a region of semiconductor material of a second conductivity type includes forming a recess having a surface, forming a dielectric material over a portion of the surface of the recess, and back-filling the recess to from a source/drain terminal.

公开(公告)号：AT373320T

公开(公告)日：2007-09-15

申请号：AT00992349

申请日：2000-11-27

Applicant: INTEL CORP

Inventor： MURTHY ANAND ,  CHAU ROBERT ,  MORROW PATRICK ,  MCFADDEN ROBERT

IPC: H01L29/06 ,  H01L21/3065 ,  H01L21/336

Abstract: A microelectronic structure includes at least one source/drain terminal of a first conductivity type that is partially isolated from a region of semiconductor material of a second conductivity type. In a further aspect of the invention, a process for forming a microelectronic structure, such as a MOSFET, having at least one source/drain terminal of a first conductivity type that is partially isolated from a region of semiconductor material of a second conductivity type includes forming a recess having a surface, forming a dielectric material over a portion of the surface of the recess, and back-filling the recess to from a source/drain terminal.