公开(公告)号：KR20180020265A

公开(公告)日：2018-02-27

申请号：KR20187002103

申请日：2015-06-24

Applicant: INTEL CORP

Inventor： NELSON DONALD W ,  MORROW PATRICK ,  BURNS STEVEN M

IPC: H01L27/02 ,  G06F17/50 ,  H01L27/118

CPC classification number: H01L27/0207 ,  G06F17/5068 ,  H01L27/11807

Abstract: 교대하는전도성라인들을갖는라이브러리셀들을이용하는집적회로레이아웃이설명된다. 일실시예는제1 셀및 제2 셀을포함하고, 제2 셀은제1 셀에인접한다. 제1 셀은제1 복수의전도성라인들을가지고, 제1 복수의제1 부분은제2 셀로부터제1 거리인라인단부들을가진다. 제2 셀은제2 복수의전도성라인들을가지고, 전도성라인들은제1 셀에서의전도성라인들에대해평행하고전도성라인들과정렬되고, 제2 복수의제2 부분은제1 셀로부터제2 거리인라인단부들을가진다. 제1 거리는제2 거리보다더 짧다.

Abstract translation: 描述了使用具有交替导电线的库单元的集成电路布局。 一个实施例包括第一小区和第二小区，并且第二小区与第一小区相邻。 第一单元具有第一多个导电线并且第一多个第一部分具有距第二单元的第一距离直列式端部。 第二单元具有第二多个导电线，导电线平行于第一单元中的导电线并且与导电线对齐，第二多个的第二部分距离第一单元的第二距离， 它的端部。 第一距离比第二距离短。

公开(公告)号：KR20180021147A

公开(公告)日：2018-02-28

申请号：KR20187002456

申请日：2015-06-26

Applicant: INTEL CORP

Inventor： JUN KIMIN ,  JENSEN JACOB M ,  MORROW PATRICK ,  FISCHER PAUL B

IPC: H01L25/16 ,  H01L25/065 ,  H01L25/07

CPC classification number: H01L25/16 ,  H01L25/0655 ,  H01L25/072 ,  H01L2224/95001

Abstract: 방법은디바이스기판을캐리어기판에커플링하는단계; 디바이스기판의일 부분을호스트기판과정렬시키는단계; 캐리어기판으로부터디바이스기판의부분을분리하는단계; 및디바이스기판의부분을분리한후에, 디바이스기판의부분을호스트기판에커플링하는단계를포함한다. 방법은디바이스기판의디바이스면과캐리어기판사이의접착제로디바이스기판을캐리어기판에커플링하는단계; 디바이스기판을캐리어기판에커플링한후에, 디바이스기판을박형화하는단계; 박형화된디바이스기판의일 부분을호스트기판과정렬시키는단계; 캐리어기판으로부터디바이스기판의부분을분리하는단계; 및디바이스기판의분리된부분을호스트기판에커플링하는단계를포함한다. 장치는적층배열로호스트기판에커플링되는디바이스층 및서브마이크론두께를포함하는기판을포함한다.

Abstract translation: 该方法包括将器件衬底耦合到载体衬底; 使器件衬底的一部分与主衬底对准; 将器件衬底的一部分与载体衬底分离; 并且在分离器件衬底的该部分之后将器件衬底的该部分耦合到主衬底。 该方法包括利用装置衬底的器件侧和载体衬底之间的粘合剂将器件衬底耦合到载体衬底; 将器件衬底耦合到载体衬底，然后减薄器件衬底; 使一部分减薄的器件衬底与主衬底对准; 将器件衬底的一部分与载体衬底分离; 并且将器件衬底的单独部分耦合到主衬底。 该设备包括衬底，该衬底包括以堆叠布置耦合到主衬底的器件层和亚微米厚度。

公开(公告)号：KR20180018497A

公开(公告)日：2018-02-21

申请号：KR20177032875

申请日：2015-06-17

Applicant: INTEL CORP

Inventor： MEHANDRU RISHABH ,  MORROW PATRICK ,  KUMAR RANJITH ,  WEBER CORY E ,  KIM SEIYON ,  CEA STEPHEN M ,  GHANI TAHIR

IPC: H01L27/06 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L29/78 ,  H01L21/8221 ,  H01L21/823821 ,  H01L27/0688

Abstract: 반도체디바이스의면적스케일링을위한수직집적방식및 회로요소아키텍쳐가설명된다. 한예에서, 인버터구조물은상위영역및 하위영역으로수직으로분리된반도체핀을포함한다. 제1 복수의게이트구조물은반도체핀의상위영역을제어하기위해포함된다. 제2 복수의게이트구조물은반도체핀의하위영역을제어하기위해포함된다. 제2 복수의게이트구조물은제1 복수의게이트구조물의도전형과는반대의도전형을갖는다.

Abstract translation: 描述了用于半导体器件的面积缩放的垂直集成方案和电路元件体系结构。 在一个示例中，逆变器结构包括垂直分离成上部区域和下部区域的半导体引脚。 包括第一多个栅极结构以控制半导体鳍的上部区域。 包括第二多个栅极结构以控制半导体鳍的子区域。 第二多个栅极结构具有与第一多个栅极结构的导电性相反的导电性。

公开(公告)号：WO2011126925A2

公开(公告)日：2011-10-13

申请号：PCT/US2011030808

申请日：2011-03-31

Applicant: INTEL CORP ,  MA QING ,  HE JUN ,  MORROW PATRICK ,  FISCHER PAUL B ,  BALAKRISHNAN SRIDHAR ,  RADHAKRISHNAN SATISH ,  ANDRYUSHCHENKO TATYANA TANYA ,  XU GUANGHAI

Inventor： MA QING ,  HE JUN ,  MORROW PATRICK ,  FISCHER PAUL B ,  BALAKRISHNAN SRIDHAR ,  RADHAKRISHNAN SATISH ,  ANDRYUSHCHENKO TATYANA TANYA ,  XU GUANGHAI

IPC: H05K3/32 ,  H05K1/18

CPC classification number: H01L24/19 ,  B23K1/0016 ,  H01L21/0334 ,  H01L24/11 ,  H01L2224/245 ,  H01L2924/01322 ,  H01L2924/14 ,  H05K3/4015 ,  H05K2201/1028 ,  H01L2924/00

Abstract: The present subject matter relates to the field of fabricating microelectronic devices. In at least one embodiment, the present subject matter relates to forming an interconnect that has a portion thereof which becomes debonded from the microelectronic device during cooling after attachment to an external device. The debonded portion allows the interconnect to flex and absorb stress.

Abstract translation: 本主题涉及制造微电子器件的领域。 在至少一个实施例中，本主题涉及形成具有其部分的互连，其在附接到外部设备之后在冷却期间从微电子器件脱粘。 脱粘部分允许互连件弯曲并吸收应力。

公开(公告)号：WO2011084216A3

公开(公告)日：2011-09-09

申请号：PCT/US2010054931

申请日：2010-11-01

Applicant: INTEL CORP ,  MA QING ,  HU CHUAN ,  MORROW PATRICK

Inventor： MA QING ,  HU CHUAN ,  MORROW PATRICK

IPC: H01L23/485 ,  H05K3/46

CPC classification number: H01L23/49822 ,  B32B2457/08 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/3675 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01016 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/05442 ,  H01L2924/14 ,  H01L2924/15184 ,  H01L2924/15788 ,  H01L2924/16251 ,  H05K3/42 ,  H05K3/4605 ,  H05K2201/0195 ,  H05K2201/096 ,  Y10T156/10 ,  H01L2924/00

Abstract: Disclosed are embodiments of a substrate for an integrated circuit (IC) device. The substrate includes a core comprised of two or more discrete glass layers that have been bonded together. A separate bonding layer may be disposed between adjacent glass layers to couple these layers together. The substrate may also include build-up structures on opposing sides of the multi-layer glass core, or perhaps on one side of the core. Electrically conductive terminals may be formed on both sides of the substrate, and an IC die may be coupled with the terminals on one side of the substrate. The terminals on the opposing side may be coupled with a next-level component, such as a circuit board. One or more conductors extend through the multi-layer glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the core. Other embodiments are described and claimed.

Abstract translation: 公开了用于集成电路（IC）器件的衬底的实施例。 衬底包括由两个或更多个已经粘合在一起的分立的玻璃层组成的芯。 单独的结合层可以设置在相邻的玻璃层之间以将这些层结合在一起。 衬底还可以包括在多层玻璃芯的相对侧上的堆积结构，或者可能在芯的一侧上。 导电端子可以形成在基板的两侧，并且IC管芯可以与基板的一侧上的端子耦合。 相对侧上的端子可以与诸如电路板的下一级组件耦合。 一个或多个导体延伸穿过多层玻璃芯，并且一个或多个导体可以与设置在芯上的积层结构电耦合。 描述并要求保护其他实施例。

公开(公告)号：WO2007050754A2

公开(公告)日：2007-05-03

申请号：PCT/US2006041779

申请日：2006-10-24

Applicant: INTEL CORP ,  BASKARAN RAJASHREE ,  RAMANATHAN SHRIRAM ,  MORROW PATRICK

Inventor： BASKARAN RAJASHREE ,  RAMANATHAN SHRIRAM ,  MORROW PATRICK

IPC: H01L23/367 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L21/76898 ,  H01L23/3677 ,  H01L23/3735 ,  H01L23/481 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/06181 ,  H01L2224/13 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2924/0002 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Some embodiments of the present invention include apparatuses and methods relating to stacked wafer or die packaging with enhanced thermal and device performance.

Abstract translation: 本发明的一些实施例包括与具有增强的热和器件性能的堆叠晶片或管芯封装相关的装置和方法。

公开(公告)号：WO03028092A3

公开(公告)日：2003-08-28

申请号：PCT/US0231159

申请日：2002-09-27

Applicant: INTEL CORP

Inventor： WONG LAWRENCE ,  MORROW PATRICK ,  LEU JIHPERNG ,  OTT ANDREW ,  KLOSTER GRANT

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76807 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A dual damascene process where first alternate ILDs (19, 21, 30, 32) are made of a first material and second alternate ILDs (20, 31, 33) are made of a second material. Each material is etchable at a faster rate than the other in the presence of different etchant such as for an organic polymer and an inorganic low K material. This allows the ILDs to be deposited alternately on one another without an etchant stop layer thereby reducing capacitance.

Abstract translation: 一种双镶嵌工艺，其中第一替代ILD（19,21,30,32）由第一材料制成，而第二替代ILD（20,31,33）由第二材料制成。 在不同的蚀刻剂（例如有机聚合物和无机低K材料）的存在下，每种材料可以以比另一种更快的速度进行刻蚀。 这允许ILD彼此交替沉积而没有蚀刻剂停止层，从而降低电容。

公开(公告)号：WO0150535A3

公开(公告)日：2002-02-07

申请号：PCT/US0042279

申请日：2000-11-27

Applicant: INTEL CORP ,  MURTHY ANAND S ,  CHAU ROBERT S ,  MORROW PATRICK ,  MCFADDEN ROBERT S

Inventor： MURTHY ANAND S ,  CHAU ROBERT S ,  MORROW PATRICK ,  MCFADDEN ROBERT S

IPC: H01L21/336 ,  H01L29/06 ,  H01L21/3065

CPC classification number: H01L29/66628 ,  H01L29/0653 ,  H01L29/66636

Abstract: A microelectronic structure includes at least one source/drain terminal of a first conductivity type that is partially isolated from a region of semiconductor material of a second conductivity type. In a further aspect of the invention, a process for forming a microelectronic structure, such as a MOSFET, having at least one source/drain terminal of a first conductivity type that is partially isolated from a region of semiconductor material of a second conductivity type includes forming a recess having a surface, forming a dielectric material over a portion of the surface of the recess, and back-filling the recess to form a source/drain terminal.

Abstract translation: 微电子结构包括与第二导电类型的半导体材料的区域部分隔离的第一导电类型的至少一个源极/漏极端子。 在本发明的另一方面，用于形成诸如MOSFET的微电子结构的方法具有至少一个与第二导电类型的半导体材料的区域部分隔离的第一导电类型的源极/漏极端子，包括 形成具有表面的凹部，在所述凹部的所述表面的一部分上形成电介质材料，并且对所述凹部进行后填充以形成源极/漏极端子。

公开(公告)号：EP3084806A4

公开(公告)日：2017-07-26

申请号：EP13899945

申请日：2013-12-18

Applicant: INTEL CORP

Inventor： JUN KIMIN ,  MORROW PATRICK

IPC: H01L21/8258 ,  H01L27/12 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/1054 ,  H01L21/02524 ,  H01L21/02538 ,  H01L21/02551 ,  H01L21/76283 ,  H01L21/823412 ,  H01L21/8258 ,  H01L27/0922 ,  H01L27/1207 ,  H01L29/16 ,  H01L29/20 ,  H01L29/22 ,  H01L29/267 ,  H01L29/78

Abstract: In an embodiment a second semiconductor layer is transferred (e.g., using layer transfer techniques) on top of a first semiconductor layer. The second layer is patterned into desired wells. Between the wells, the first layer is exposed. The exposed first layer is epitaxially grown to the level of the transferred second layer to complete a planar heterogeneous substrate including both S1 and S2. The heterogeneous materials may be utilized such that, for example, a P channel device formed from one of III-V or IV materials is coplanar with an N channel device formed from one of III-V or IV materials. The embodiment requires no lattice parameter compliance due to the second layer being transferred onto the first layer. Also, there is no (or little) buffer and/or hetero-epitaxy. Other embodiments are described herein.

Abstract translation: 在一个实施例中，第二半导体层在第一半导体层上被转移（例如，使用层转移技术）。 第二层被图案化成所需的孔。 在井之间，第一层被暴露。 暴露的第一层外延生长到转移的第二层的水平以完成包括S1和S2两者的平面异质衬底。 可以使用非均质材料，使得例如由III-V或IV材料中的一种形成的P沟道器件与由III-V或IV材料中的一种形成的N沟道器件共面。 由于第二层被转移到第一层上，该实施例不需要晶格参数顺从性。 此外，没有（或很少）缓冲和/或异质外延。 这里描述了其他实施例。

公开(公告)号：EP3155666A4

公开(公告)日：2018-03-14

申请号：EP14895397

申请日：2014-09-27

Applicant: INTEL CORP

Inventor： NELSON DONALD W ,  MORROW PATRICK ,  JUN KIMIN

IPC: H01L29/78 ,  H01L21/335 ,  H01L21/768 ,  H01L23/00 ,  H01L23/528

CPC classification number: H01L23/5283 ,  H01L21/76838 ,  H01L24/14 ,  H01L29/78 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method including forming a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein the plurality of second interconnects include interconnects of different dimensions; and forming contact points to the second plurality of interconnects, the contact points operable for connection to an external source. An apparatus including a substrate including a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein the plurality of second interconnects include interconnects of different dimensions; and contact points coupled to the second plurality of interconnects, the contact points operable for connection to an external source.