公开(公告)号：US12242846B2

公开(公告)日：2025-03-04

申请号：US18618648

申请日：2024-03-27

Applicant: Intel Corporation

Inventor： Naveen Mellempudi ,  Subramaniam Maiyuran ,  Varghese George ,  Fangwen Fu ,  Shuai Mu ,  Supratim Pal ,  Wei Xiong

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F17/16 ,  G06N20/00

Abstract: An apparatus to facilitate supporting 8-bit floating point format operands in a computing architecture is disclosed. The apparatus includes a processor comprising: a decoder to decode an instruction fetched for execution into a decoded instruction, wherein the decoded instruction is a matrix instruction that operates on 8-bit floating point operands to cause the processor to perform a parallel dot product operation; a controller to schedule the decoded instruction and provide input data for the 8-bit floating point operands in accordance with an 8-bit floating data format indicated by the decoded instruction; and systolic dot product circuitry to execute the decoded instruction using systolic layers, each systolic layer comprises one or more sets of interconnected multipliers, shifters, and adder, each set of multipliers, shifters, and adders to generate a dot product of the 8-bit floating point operands.

公开(公告)号：US20250068423A1

公开(公告)日：2025-02-27

申请号：US18453861

申请日：2023-08-22

Applicant: Intel Corporation

Inventor： Jorge Eduardo Parra Osorio ,  Jiasheng Chen ,  Supratim Pal ,  Vasanth Ranganathan ,  Guei-Yuan Lueh ,  James Valerio ,  Pradeep Golconda ,  Brent Schwartz ,  Fangwen Fu ,  Sabareesh Ganapathy ,  Peter Caday ,  Wei-Yu Chen ,  Po-Yu Chen ,  Timothy Bauer ,  Maxim Kazakov ,  Stanley Gambarin ,  Samir Pandya

IPC: G06F9/30 ,  G06F9/38

Abstract: Described herein is a graphics processor comprising first circuitry configured to execute a decoded instruction and second circuitry configured to second circuitry configured to decode an instruction into the decoded instruction. The second circuitry is configured to determine a number of registers within a register file that are available to a thread of the processing resource and decode the instruction based on that number of registers.

公开(公告)号：US20250037347A1

公开(公告)日：2025-01-30

申请号：US18358297

申请日：2023-07-25

Applicant: Intel Corporation

Inventor： Jiasheng Chen ,  Supratim Pal ,  Kevin Hurd ,  Jorge E. Parra Osorio ,  Christopher Spencer ,  Takashi Nakagawa ,  Guei-Yuan Lueh ,  Pradeep K. Golconda ,  James Valerio ,  Mukundan Swaminathan ,  Nicholas Murphy ,  Clifford Gibson ,  Li-An Tang ,  Fangwen Fu ,  Kaiyu Chen ,  Buqi Cheng

IPC: G06T15/00 ,  G06F9/30

Abstract: Described herein is a graphics processor comprising an instruction cache and a plurality of processing elements coupled with the instruction cache. The plurality of processing elements include functional units configured to provide an integer pipeline to execute instructions to perform operations on integer data elements. The integer pipeline including a first multiplier and a second multiplier, the first multiplier and the second multiplier configured to execute operations for a single instruction.

公开(公告)号：US12039001B2

公开(公告)日：2024-07-16

申请号：US18301386

申请日：2023-04-17

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Jorge Parra ,  Supratim Pal ,  Ashutosh Garg ,  Shubra Marwaha ,  Chandra Gurram ,  Darin Starkey ,  Durgesh Borkar ,  Varghese George

IPC: G06F17/16 ,  G06F9/30 ,  G06F15/80

CPC classification number: G06F17/16 ,  G06F9/3001 ,  G06F9/30145 ,  G06F15/8046

Abstract: Described herein is a graphics processor including a plurality of processing clusters coupled with a host interface, each processing cluster comprising a plurality of multiprocessors, the plurality of multiprocessors interconnected via a data interconnect, and each multiprocessor comprising sparse matrix multiply acceleration hardware including a systolic processing array with feedback inputs.

公开(公告)号：US11977885B2

公开(公告)日：2024-05-07

申请号：US17107823

申请日：2020-11-30

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Jorge Parra ,  Ashutosh Garg ,  Chandra Gurram ,  Chunhui Mei ,  Durgesh Borkar ,  Shubra Marwaha ,  Supratim Pal ,  Varghese George ,  Wei Xiong ,  Yan Li ,  Yongsheng Liu ,  Dipankar Das ,  Sasikanth Avancha ,  Dharma Teja Vooturi ,  Naveen K. Mellempudi

IPC: G06F9/30 ,  G06F9/38 ,  G06F15/80

CPC classification number: G06F9/30036 ,  G06F9/3001 ,  G06F9/30101 ,  G06F9/3893 ,  G06F15/8046

Abstract: An apparatus to facilitate utilizing structured sparsity in systolic arrays is disclosed. The apparatus includes a processor comprising a systolic array to receive data from a plurality of source registers, the data comprising unpacked source data, structured source data that is packed based on sparsity, and metadata corresponding to the structured source data; identify portions of the unpacked source data to multiply with the structured source data, the portions of the unpacked source data identified based on the metadata; and output, to a destination register, a result of multiplication of the portions of the unpacked source data and the structured source data.

公开(公告)号：US11900502B2

公开(公告)日：2024-02-13

申请号：US17734983

申请日：2022-05-02

Applicant: Intel Corporation

Inventor： Chandra S. Gurram ,  Gang Y. Chen ,  Subramaniam Maiyuran ,  Supratim Pal ,  Ashutosh Garg ,  Jorge E. Parra ,  Darin M. Starkey ,  Guei-Yuan Lueh ,  Wei-Yu Chen

IPC: G06T1/20 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06T1/60

Abstract: Examples described herein relate to a software and hardware optimization that manages scenarios where a write operation to a register is less than an entirety of the register. A compiler detects instructions that make partial writes to the same register, groups such instructions, and provides hints to hardware of the partial write. The execution unit combines the output data for grouped instructions and updates the destination register as single write instead of multiple separate partial writes.

公开(公告)号：US20230367740A1

公开(公告)日：2023-11-16

申请号：US18310129

申请日：2023-05-01

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Jorge Parra ,  Supratim Pal ,  Chandra Gurram

IPC: G06F15/80

CPC classification number: G06F15/8046 ,  G06F15/8007 ,  G06N20/00

Abstract: An apparatus to facilitate computing efficient cross channel operations in parallel computing machines using systolic arrays is disclosed. The apparatus includes a plurality of registers and one or more processing elements communicably coupled to the plurality of registers. The one or more processing elements include a systolic array circuit to perform cross-channel operations on source data received from a single source register of the plurality of registers, wherein the systolic array circuit is modified to: receive inputs from the single source register at different stages of the systolic array circuit; perform cross-channel operations at channels of the systolic array circuit; bypass disabled channels of the systolic array circuit, the disabled channels not used to compute the cross-channel operations; and broadcast a final result of a final stage of the systolic array circuit to all channels of a destination register.

公开(公告)号：US20230153176A1

公开(公告)日：2023-05-18

申请号：US17528386

申请日：2021-11-17

Applicant: Intel Corporation

Inventor： Chunhui Mei ,  James Valerio ,  Supratim Pal ,  Guei-Yuan Lueh ,  Hong Jiang

IPC: G06F9/52 ,  G06F9/48

CPC classification number: G06F9/522 ,  G06F9/48

Abstract: An apparatus to facilitate facilitating forward progress guarantee using single-level synchronization at individual thread granularity is disclosed. The apparatus includes a processor comprising a barrier synchronization hardware circuitry to assign a set of global named barrier identifiers (IDs) to individual execution threads of a plurality of execution threads and synchronize execution of the individual execution threads on a single level via the set of global named barrier IDs; and a plurality of processing resources to execute the plurality of execution threads and comprising divergent barrier scheduling hardware circuitry to facilitate execution flow switching from a first divergent branch executed by a first thread to a second divergent branch executed by a second thread, the execution flow switching performed responsive to the first thread stalling to wait on a named barrier of the set of global named barrier IDs.

公开(公告)号：US11636174B2

公开(公告)日：2023-04-25

申请号：US17527882

申请日：2021-11-16

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Jorge Parra ,  Supratim Pal ,  Ashutosh Garg ,  Shubra Marwaha ,  Chandra Gurram ,  Darin Starkey ,  Durgesh Borkar ,  Varghese George

IPC: G06F17/16 ,  G06F9/30 ,  G06F15/80

Abstract: Described herein is an accelerator device including a host interface, a fabric interconnect coupled with the host interface, and one or more hardware tiles coupled with the fabric interconnect, the one or more hardware tiles including sparse matrix multiply acceleration hardware including a systolic array with feedback inputs.

公开(公告)号：US20220416999A1

公开(公告)日：2022-12-29

申请号：US17358897

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Supratim Pal ,  Wajdi Feghali ,  Changwon Rhee ,  Wei-Yu Chen ,  Timothy R. Bauer ,  Alexander Lyashevsky

IPC: H04L9/06 ,  G06F9/38 ,  G06T15/00

Abstract: An apparatus to facilitate a fused instruction to accelerate performance of secure hash algorithm 2 (SHA-2) in a graphics environment is disclosed. The apparatus includes a processor comprising processing resources, the processing resources comprising execution circuitry to receive a fused SHA instruction identifying a length corresponding to a data size of the fused SHA instruction and a functional control identifying an operation type of the fused SHA instruction; based on decoding the fused SHA instruction, cause a sub-function identified by the length and the function control to be scheduled to an integer pipeline of the execution resource; and execute the sub-function of the fused SHA instruction in an integer pipeline of the execution circuitry, the sub-function to perform merged operations on a source operand of the fused SHA instruction, the merged operations comprising a rotate operation, a shift operation, and an xor operation.