公开(公告)号：US12014183B2

公开(公告)日：2024-06-18

申请号：US17949904

申请日：2022-09-21

Applicant: Intel Corporation

Inventor： John Wiegert ,  Joydeep Ray ,  Timothy Bauer ,  James Valerio

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/355 ,  G06F15/78

CPC classification number: G06F9/3887 ,  G06F9/355 ,  G06F15/7839 ,  G06F9/30036 ,  G06F9/30043

Abstract: Embodiments described herein provide a technique to decompose 64-bit per-lane virtual addresses to access a plurality of data elements on behalf of a multi-lane parallel processing execution resource of a graphics or compute accelerator. The 64-bit per-lane addresses are decomposed into a base address and a plurality of per-lane offsets for transmission to memory access circuitry. The memory access circuitry then combines the base address and the per-lane offsets to reconstruct the per-lane addresses.

公开(公告)号：US20240095038A1

公开(公告)日：2024-03-21

申请号：US17949904

申请日：2022-09-21

Applicant: Intel Corporation

Inventor： John Wiegert ,  Joydeep Ray ,  Timothy Bauer ,  James Valerio

IPC: G06F15/78 ,  G06F9/30

CPC classification number: G06F15/7839 ,  G06F9/30043

Abstract: Embodiments described herein provide a technique to decompose 64-bit per-lane virtual addresses to access a plurality of data elements on behalf of a multi-lane parallel processing execution resource of a graphics or compute accelerator. The 64-bit per-lane addresses are decomposed into a base address and a plurality of per-lane offsets for transmission to memory access circuitry. The memory access circuitry then combines the base address and the per-lane offsets to reconstruct the per-lane addresses.

公开(公告)号：US20250068423A1

公开(公告)日：2025-02-27

申请号：US18453861

申请日：2023-08-22

Applicant: Intel Corporation

Inventor： Jorge Eduardo Parra Osorio ,  Jiasheng Chen ,  Supratim Pal ,  Vasanth Ranganathan ,  Guei-Yuan Lueh ,  James Valerio ,  Pradeep Golconda ,  Brent Schwartz ,  Fangwen Fu ,  Sabareesh Ganapathy ,  Peter Caday ,  Wei-Yu Chen ,  Po-Yu Chen ,  Timothy Bauer ,  Maxim Kazakov ,  Stanley Gambarin ,  Samir Pandya

IPC: G06F9/30 ,  G06F9/38

Abstract: Described herein is a graphics processor comprising first circuitry configured to execute a decoded instruction and second circuitry configured to second circuitry configured to decode an instruction into the decoded instruction. The second circuitry is configured to determine a number of registers within a register file that are available to a thread of the processing resource and decode the instruction based on that number of registers.

公开(公告)号：US20240330001A1

公开(公告)日：2024-10-03

申请号：US18620217

申请日：2024-03-28

Applicant: Intel Corporation

Inventor： John Wiegert ,  Joydeep Ray ,  Timothy Bauer ,  James Valerio

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/355 ,  G06F15/78

CPC classification number: G06F9/3887 ,  G06F9/355 ,  G06F15/7839 ,  G06F9/30036 ,  G06F9/30043

Abstract: Embodiments described herein provide a technique to decompose 64-bit per-lane virtual addresses to access a plurality of data elements on behalf of a multi-lane parallel processing execution resource of a graphics or compute accelerator. The 64-bit per-lane addresses are decomposed into a base address and a plurality of per-lane offsets for transmission to memory access circuitry. The memory access circuitry then combines the base address and the per-lane offsets to reconstruct the per-lane addresses.

公开(公告)号：US20240160478A1

公开(公告)日：2024-05-16

申请号：US17987185

申请日：2022-11-15

Applicant: Intel Corporation

Inventor： Jiasheng Chen ,  Chunhui Mei ,  Ben J. Ashbaugh ,  Naveen Matam ,  Joydeep Ray ,  Timothy Bauer ,  Guei-Yuan Lueh ,  Vasanth Ranganathan ,  Prashant Chaudhari ,  Vikranth Vemulapalli ,  Nishanth Reddy Pendluru ,  Piotr Reiter ,  Jain Philip ,  Marek Rudniewski ,  Christopher Spencer ,  Parth Damani ,  Prathamesh Raghunath Shinde ,  John Wiegert ,  Fataneh Ghodrat

IPC: G06F9/50 ,  G06F12/0875

CPC classification number: G06F9/5016 ,  G06F12/0875 ,  G06F2212/452

Abstract: An apparatus to facilitate increasing processing resources in processing cores of a graphics environment is disclosed. The apparatus includes a plurality of processing resources to execute one or more execution threads; a plurality of message arbiter-processing resource (MA-PR) routers, wherein a respective MA-PR router of the plurality of MA-PR routers corresponds to a pair of processing resources of the plurality of processing resources and is to arbitrate routing of a thread control message from a message arbiter between the pair of processing resources; a plurality of local shared cache (LSC) sequencers to provide an interface between at least one LSC of the processing core and the plurality of processing resources; and a plurality of instruction caches (ICs) to store instructions of the one or more execution threads, wherein a respective IC of the plurality of ICs interfaces with a portion of the plurality of processing resources.

公开(公告)号：US20240086064A1

公开(公告)日：2024-03-14

申请号：US17944500

申请日：2022-09-14

Applicant: Intel Corporation

Inventor： John Wiegert ,  Joydeep Ray ,  Timothy Bauer ,  James Valerio

IPC: G06F3/06 ,  G06T1/20 ,  G06T1/60

CPC classification number: G06F3/0604 ,  G06F3/0644 ,  G06F3/0673 ,  G06T1/20 ,  G06T1/60

Abstract: Embodiments described herein enable the offload of address calculations required to access a data element within an array of data elements from primary compute resources of a graphics processor to the memory access circuitry of the graphics processor. The memory access circuitry is configured to receive a message to access a data element of an array of data elements in the memory, the message to include an index of the data element in the array of data elements, calculate a byte address for the data element based in part on the index of the data element in the array of data elements, and submit a memory access request to the memory to access the data element at the byte address.