公开(公告)号：US12142689B2

公开(公告)日：2024-11-12

申请号：US17940949

申请日：2022-09-08

Applicant: Intel Corporation

Inventor： Sean Ma ,  Abhishek Sharma ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Van H. Le

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/417 ,  H01L29/49 ,  H01L29/78

Abstract: A transistor is described. The transistor includes a substrate, a first semiconductor structure above the substrate, a second semiconductor structure above the substrate, a source contact that includes a first metal structure that contacts a plurality of surfaces of the first semiconductor structure and a drain contact that includes a second metal structure that contacts a plurality of surfaces of the second semiconductor structure. The transistor also includes a gate below a back side of the substrate.

公开(公告)号：US12125917B2

公开(公告)日：2024-10-22

申请号：US18227233

申请日：2023-07-27

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Van H. Le ,  Jack T. Kavalieros ,  Tahir Ghani ,  Gilbert Dewey

IPC: H01L29/786 ,  H01L29/423

CPC classification number: H01L29/78648 ,  H01L29/42384 ,  H01L29/78603 ,  H01L2029/42388 ,  H01L29/78672 ,  H01L29/7869

Abstract: Thin film transistors having double gates are described. In an example, an integrated circuit structure includes an insulator layer above a substrate. A first gate stack is on the insulator layer. A polycrystalline channel material layer is on the first gate stack. A second gate stack is on a first portion of the polycrystalline channel material layer, the second gate stack having a first side opposite a second side. A first conductive contact is adjacent the first side of the second gate stack, the first conductive contact on a second portion of the channel material layer. A second conductive contact is adjacent the second side of the second gate stack, the second conductive contact on a third portion of the channel material layer.

公开(公告)号：US12119409B2

公开(公告)日：2024-10-15

申请号：US18345641

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Van H. Le ,  Abhishek A. Sharma ,  Gilbert Dewey ,  Kent Millard ,  Jack Kavalieros ,  Shriram Shivaraman ,  Tristan A. Tronic ,  Sanaz Gardner ,  Justin R. Weber ,  Tahir Ghani ,  Li Huey Tan ,  Kevin Lin

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/66 ,  H01L29/267

CPC classification number: H01L29/78693 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/66969 ,  H01L29/78696 ,  H01L29/267

Abstract: An integrated circuit includes: a gate dielectric; a first layer adjacent to the gate dielectric; a second layer adjacent to the first layer, the second layer comprising an amorphous material; a third layer adjacent to the second layer, the third layer comprising a crystalline material; and a source or drain at least partially adjacent to the third layer. In some cases, the crystalline material of the third layer is a first crystalline material, and the first layer comprises a second crystalline material, which may be the same as or different from the first crystalline material. In some cases, the gate dielectric includes a high-K dielectric material. In some cases, the gate dielectric, the first layer, the second layer, the third layer, and the source or drain are part of a back-gate transistor structure (e.g., back-gate TFT), which may be part of a memory structure (e.g., located within an interconnect structure).

公开(公告)号：US12080605B2

公开(公告)日：2024-09-03

申请号：US17866122

申请日：2022-07-15

Applicant: INTEL CORPORATION

Inventor： Aaron D. Lilak ,  Ehren Mannebach ,  Anh Phan ,  Richard E. Schenker ,  Stephanie A. Bojarski ,  Willy Rachmady ,  Patrick R. Morrow ,  Jeffrey D. Bielefeld ,  Gilbert Dewey ,  Hui Jae Yoo

IPC: H01L21/8234 ,  H01L23/48 ,  H01L23/532 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L21/823475 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L23/481 ,  H01L23/53295 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/785

Abstract: Backside contact structures include etch selective materials to facilitate backside contact formation. An integrated circuit structure includes a frontside contact region, a device region below the frontside contact region, and a backside contact region below the device region. The device region includes a transistor. The backside contact region includes a first dielectric material under a source or drain region of the transistor, a second dielectric material laterally adjacent to the first dielectric material and under a gate structure of the transistor. A non-conductive spacer is between the first and second dielectric materials. The first and second dielectric materials are selectively etchable with respect to one another and the spacer. The backside contact region may include an interconnect feature that, for instance, passes through the first dielectric material and contacts a bottom side of the source/drain region, and/or passes through the second dielectric material and contacts the gate structure.

公开(公告)号：US20240186127A1

公开(公告)日：2024-06-06

申请号：US18399237

申请日：2023-12-28

Applicant: Intel Corporation

Inventor： Ilya V. Karpov ,  Aaron A. Budrevich ,  Gilbert Dewey ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Dan S. Lavric

IPC: H01J37/34 ,  C23C14/34 ,  H01L21/285 ,  H01L29/08 ,  H01L29/45

CPC classification number: H01J37/3426 ,  C23C14/3414 ,  H01L21/28518 ,  H01L21/28568 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/456 ,  H01J2237/332

Abstract: An integrated circuit structure includes a source or drain region, and a contact coupled to the source or drain region. Sputter targets that include metals doped with the appropriate dopant types are used to deposit a conductive layer on the source or drain region that is annealed to form a region including metals and semiconductor materials between the source or drain region and the contact. A first dopant is within the source or drain region, and a second dopant is within the region. In one example, the first dopant is elementally different from the second dopant. In another example, the first dopant is elementally the same as the second dopant, wherein a concentration of the first dopant within a section of the source or drain region is within 20% of a concentration of the second dopant within the region.

公开(公告)号：US20240105852A1

公开(公告)日：2024-03-28

申请号：US18533436

申请日：2023-12-08

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Sean T. Ma ,  Van H. Le ,  Jack T. Kavalieros ,  Gilbert Dewey

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/78675 ,  H01L29/0649 ,  H01L29/42364 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66757 ,  H01L29/66969 ,  H01L29/78666 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/7869 ,  H01L29/78696

Abstract: Top-gate thin film transistor (TFTs) structures. Thin film transistors when in the top-gate configuration suffer from contact resistance. An example TFT includes a semiconductor layer doped with one or more dopant elements. A gate dielectric layer is on the semiconductor layer, and a gate electrode is on the gate dielectric layer. The semiconductor layer is doped with the one or more dopant elements beneath the gate dielectric layer. The TFT may further include one or more contacts and/or one or more gate spacers, and the semiconductor layer may further be doped with the one or more dopant elements beneath the contact(s) and/or gate spacer(s).

公开(公告)号：US11929320B2

公开(公告)日：2024-03-12

申请号：US17709032

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Ryan Keech ,  Cory Bomberger ,  Cheng-Ying Huang ,  Ashish Agrawal ,  Willy Rachmady ,  Anand Murthy

IPC: H01L29/74 ,  H01L21/762 ,  H01L21/768 ,  H01L23/522 ,  H01L27/12

CPC classification number: H01L23/5226 ,  H01L21/76251 ,  H01L21/76804 ,  H01L27/1203

Abstract: A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.

公开(公告)号：US11894372B2

公开(公告)日：2024-02-06

申请号：US18095973

申请日：2023-01-11

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Cheng-Ying Huang ,  Gilbert Dewey ,  Aaron Lilak ,  Patrick Morrow ,  Anh Phan ,  Ehren Mannebach ,  Jack T. Kavalieros

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/66545

Abstract: A device is disclosed. The device includes a first semiconductor fin, a first source-drain epitaxial region adjacent a first portion of the first semiconductor fin, a second source-drain epitaxial region adjacent a second portion of the first semiconductor fin, a first gate conductor above the first semiconductor fin, a gate spacer covering the sides of the gate conductor, a second semiconductor fin below the first semiconductor fin, a second gate conductor on a first side of the second semiconductor fin and a third gate conductor on a second side of the second semiconductor fin, a third source-drain epitaxial region adjacent a first portion of the second semiconductor fin, and a fourth source-drain epitaxial region adjacent a second portion of the second semiconductor fin. The device also includes a dielectric isolation structure below the first semiconductor fin and above the second semiconductor fin that separates the first semiconductor fin and the second semiconductor fin.

公开(公告)号：US11869890B2

公开(公告)日：2024-01-09

申请号：US16651233

申请日：2017-12-26

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Willy Rachmady ,  Gilbert Dewey ,  Rishabh Mehandru ,  Jack T. Kavalieros

IPC: H01L27/092 ,  H01L21/768 ,  H01L21/822 ,  H01L23/485 ,  H01L27/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823871 ,  H01L23/485 ,  H01L27/0688

Abstract: An apparatus is provided which comprises: a first transistor comprising a source region and a drain region with a channel region therebetween, a first dielectric layer over the first transistor, a second transistor comprising a source region and a drain region with a channel region therebetween, wherein the second transistor is over the first dielectric layer, a second dielectric layer over the second transistor, and a contact coupled to the source region or the drain region of the first transistor, wherein the contact comprises a metal having a straight sidewall that extends from through both the first and second dielectric layers. Other embodiments are also disclosed and claimed.

公开(公告)号：US20240006506A1

公开(公告)日：2024-01-04

申请号：US17856979

申请日：2022-07-02

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Siddharth Chouksey ,  Nazila Haratipour ,  Christopher Jezewski ,  Jitendra Kumar Jha ,  Ilya V. Karpov ,  Jack T. Kavalieros ,  Arnab Sen Gupta ,  I-Cheng Tung ,  Nancy Zelick ,  Chi-Hing Choi ,  Dan S. Lavric

IPC: H01L29/45 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L29/458 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/7851 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/401

Abstract: Contacts to n-type source/drain regions comprise a phosphide or arsenide metal compound layer. The phosphide or arsenide metal compound layers can aid in forming thermally stable low resistance contacts. A phosphide or arsenide metal compound layer is positioned between the source/drain region and the contact metal layer of the contact. A phosphide or arsenic metal compound layer can be used in contacts contacting n-type source/drain regions comprising phosphorous or arsenic as the primary dopant, respectively. The phosphide or arsenide metal compound layers prevent diffusion of phosphorous or arsenic from the source/drain region into the metal contact layer and dopant deactivation in the source/drain region due to annealing and other high-temperature processing steps that occur after contact formation. Phosphide and arsenide metal contact layers can also reduce the amount of silicide that forms in source/drain regions during processing by limiting the amount of contact metal that diffuses into source/drain regions.