公开(公告)号：JPH10335446A

公开(公告)日：1998-12-18

申请号：JP14171697

申请日：1997-05-30

Applicant: MATSUSHITA ELECTRIC WORKS LTD

Inventor： OGIWARA ATSUSHI ,  OKA NAOMASA ,  OKUTO TAKASHI ,  KAMAKURA MASATOMO

IPC: H01L21/762 ,  H01L21/316

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a dielectric isolation substrate which can prevent generation of a void at a tip end of a V-shaped groove. SOLUTION: A polysilicon layer 5a is formed as deposited on a side of a single crystal silicon substrate 1 having a groove 1a made therein by a CD process using trichlorosilane and hydrogen gases as source gases. At this time, flow rates of the source gases, especially the flow rate of the trichlorosilane gas is adjusted so that a deposition rate of the polysilicon layer 5a is 2 μm/min. or less. Next, the flow rates of the source gases, especially, the flow rate of the trichlorosilane gas is increased to set the deposition rate at 2 μm/min. or more, under the condition of which an upper polysilicon layer 5b is deposited.

公开(公告)号：JPH06338607A

公开(公告)日：1994-12-06

申请号：JP12680693

申请日：1993-05-28

Applicant: MATSUSHITA ELECTRIC WORKS LTD

Inventor： OKA NAOMASA

IPC: H01L21/76 ,  H01L21/316 ,  H01L29/78 ,  H01L29/784

Abstract: PURPOSE:To provide a manufacturing method of a semiconductor device capable of notably cutting down the numbers in the manufacturing steps of MOS structured semiconductor device for the formation of gate inslating films and the separation of element region. CONSTITUTION:During the formation of a MOS integrated circuit or MOS semiconductor element on a silicon substrate, an oxynitride film 13 is formed by thermally nitriding a silicon oxide film so as to be etched away using a mask having the aperture parts on the forming positions of element separating region so that the silicon substrate 11 may be oxidized using the oxynitride film 13 as a selective oxidizing mask to simultaneously form a gate insulating films 17 (re-oxidized oxynitride film) and a field oxide films 16 in the element separating region. Through these procedures, the formation of the gate insulating films 17 and field oxide films 16 separating the element region can be simultaneously performed thereby enabling the manufacturing step numbers to be notably cut down.

公开(公告)号：JPH04348517A

公开(公告)日：1992-12-03

申请号：JP12117091

申请日：1991-05-27

Applicant: MATSUSHITA ELECTRIC WORKS LTD

Inventor： OKA NAOMASA

IPC: H01L21/28

Abstract: PURPOSE:To provide a method of easily providing a proper contact hole where an electrode comes to contact with the surface of a semiconductor substrate in a proper state. CONSTITUTION:Method of forming contact holes, characterized by forming sidewalls 11, which consist of polycrystalline semiconductors, so that the diameters of through holes may be smaller gradually as they go from the surface side to the bottoms, at the sides of the through holes after forming said through holes for holes in an insulating film 2 when providing the insulating film 2 of a semiconductor substrate 1, whose surface is covered with said insulating film 2, with holes 12a and 12b for bringing electrodes into contact with them.

公开(公告)号：JPH0260146A

公开(公告)日：1990-02-28

申请号：JP21298188

申请日：1988-08-26

Applicant: MATSUSHITA ELECTRIC WORKS LTD

Inventor： OKA NAOMASA

IPC: H01L21/76 ,  H01L21/316

Abstract: PURPOSE:To render moderate the impurity concentration distribution gradient in the end sections of a channel stopper region and to prevent an element forming region from reduction due to bird's beaks by a method wherein walls are provided on the sides or a mask in a process of field oxide film formation. CONSTITUTION:An oxide film 2' is a mask to cover an element forming region A when an impurity is supplied for the formation of a channel stopper and, on the sides of the masking oxide film 2', side walls 13 are provided. After ion implantation, a channel stopper region 11 is formed, which is accomplished simultaneously with the formation of a field oxide film 5 by thermal oxidation. With oxidation in the transverse direction being stopped at the side walls 13, birds' beaks scarcely penetrate into under the oxide film 2', which allows the element forming region A to be approximately of a specified size. In the end sections 11a of the channel stopper, impurity concentration is automatically lower at points farther from the element forming region A.

公开(公告)号：JPS6446956A

公开(公告)日：1989-02-21

申请号：JP20333387

申请日：1987-08-15

Applicant: MATSUSHITA ELECTRIC WORKS LTD

Inventor： OKA NAOMASA

IPC: H01L21/76 ,  H01L21/316

Abstract: PURPOSE:To enable the selective oxidation of a thick oxide film suitable to a field oxide film and the like for a high breakdown strength element, without deteriorating the dimensional accuracy of the field oxide film and the like, by using a mask which has a plurality of layers composed of material comparatively hard to be oxidized in the direction of thickness. CONSTITUTION:Oxidation is performed in the state where a mask 3 of arbitrary shape containing material comparatively hard to be oxidized is formed on the surface of a semiconductor. At the time of selectively oxidizing part where the mask 3 is not formed on the surface of the semicoductor 1, the following is used for the mask 3; one in which a plurality of layers 3a composed of material comparatively hard to be oxidized are contained in the direction of thickness. Thereby, the selective oxidation of a thick oxide film 5 suitable to a field oxide film and the like for a high breakdown strength element is enabled, without deteriorating dimension accuracy of the field oxide film 5 and the like.

公开(公告)号：JPS5931067A

公开(公告)日：1984-02-18

申请号：JP14133982

申请日：1982-08-14

Applicant: Matsushita Electric Works Ltd

Inventor： OKA NAOMASA ,  TANAKA YOSHIMITSU

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/78

Abstract: PURPOSE:To form a groove having a smooth groove bottom by removing a selective oxidized part and oxygen shielding films, after the substrate surface is selectively covered with the oxygen shielding films into a mask, and then a groove forming scheduled part is selectively oxidized. CONSTITUTION:The Si3N4 films 10 are deposited by vapor on the Si substrate 11, and photoetching is performed. Then, an oxygen ion implanted layer 12 is deeply provided with the films 10 as the mask. Next, an SiO2 layer 13 is formed by thermally oxidizing the layer 12. Thereafter, the layer 13 and the films 10 are removed by etching, resulting in the formation of the groove 14 of a smooth groove bottom. Then, P type diffused layers 16, N type diffused layers 17, a gate oxide film 18, and a gate electrode 19 are formed.

Abstract translation: 目的：通过去除选择性氧化部分和氧气屏蔽膜来形成具有平滑槽底的凹槽，在将氧屏蔽膜选择性地覆盖到掩模之后，然后选择性地氧化形成沟槽的部分。 构成：Si 3 N 4膜10通过蒸气沉积在Si衬底11上，并进行光刻。 然后，将氧离子注入层12设置为膜10作为掩模。 接下来，通过热氧化层12形成SiO 2层13.此后，通过蚀刻去除层13和膜10，导致形成平滑槽底的槽14。 然后，形成P型扩散层16，N型扩散层17，栅极氧化膜18和栅极电极19。

公开(公告)号：JP2006175555A

公开(公告)日：2006-07-06

申请号：JP2004371488

申请日：2004-12-22

Applicant: Matsushita Electric Works Ltd ,  松下電工株式会社

Inventor： TSUJI KOJI ,  EDA KAZUO ,  OKUTO TAKASHI ,  OKA NAOMASA ,  MIYAJIMA HISAKAZU ,  SAIJO TAKASHI ,  KIRIHARA MASAO

IPC: B81C1/00 ,  G01C19/56 ,  G01C19/5762 ,  G01C19/5769 ,  G01P15/125 ,  H01L29/84

Abstract: PROBLEM TO BE SOLVED: To provide a method of producing a minute electromechanical device in which a high-performance minute electromechanical element and a high-performance integrated circuit are integrated. SOLUTION: In producing the minute electromechanical device integrating a gyro sensor S as the minute electromechanical element and the integrated circuit 3, a silicon substrate 1A as a semiconductor substrate is arranged, and a silicon layer 1B having a resistivity higher than that of the silicon substrate 1A is formed on one surface of the silicon substrate 1A, and then the integrate circuit 3 is formed on the silicon layer 1B. Thereafter part of the silicon layer 1B on the silicon substrate 1A, that overlaps an area in which the gyro sensor S is to be formed, is removed, and the silicon substrate 1A is machined, to thereby form a three-dimensional structure forming a most part of the gyro sensor S. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 解决的问题：提供一种集成了高性能微小机电元件和高性能集成电路的微机电装置的制造方法。 解决方案：在制造将陀螺仪传感器S作为微电子机电元件和集成电路3进行集成的微机电装置时，配置有作为半导体基板的硅基板1A，并且具有电阻率高于 在硅衬底1A的一个表面上形成硅衬底1A，然后在硅层1B上形成积分电路3。 此后，除去硅衬底1A上与形成陀螺仪传感器S的区域重叠的一部分硅层1B，并加工硅衬底1A，从而形成最多的三维结构 陀螺传感器的一部分。版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2006175554A

公开(公告)日：2006-07-06

申请号：JP2004371462

申请日：2004-12-22

Applicant: Matsushita Electric Works Ltd ,  松下電工株式会社

Inventor： TSUJI KOJI ,  EDA KAZUO ,  OKUTO TAKASHI ,  OKA NAOMASA ,  MIYAJIMA HISAKAZU ,  SAIJO TAKASHI ,  KIRIHARA MASAO

IPC: B81B7/02 ,  B81B3/00

Abstract: PROBLEM TO BE SOLVED: To provide a minute electromechanical device which can enhance the performance of both a minute electromechanical element and an integrated circuit.
SOLUTION: A gyro sensor device has an element forming substrate 1, on which a gyro sensor as the minute electromechanical element and the integrated circuit 3 are formed. The element forming substrate 1 is formed of a multi-layer substrate including a silicon substrate 1A and another silicon substrate 1B arranged on one surface of the silicon substrate 1A in a thickness direction, and having a resistivity larger than that of the silicon substrate 1A. Then the gyro sensor is formed astride the silicon substrate 1A and the silicon substrate 1B, and the integrated circuit 3 is formed on the silicon substrate 1B.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种能够提高微机电元件和集成电路的性能的微小机电装置。 解决方案：陀螺传感器装置具有元件形成基板1，在其上形成作为微机电元件的陀螺仪传感器和集成电路3。 元件形成基板1由包括硅基板1A和布置在硅基板1A的一个表面上的厚度方向上的另一硅基板1B的多层基板形成，并且具有大于硅基板1A的电阻率的电阻率。 然后，陀螺仪传感器跨越硅衬底1A和硅衬底1B，并且集成电路3形成在硅衬底1B上。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2006145842A

公开(公告)日：2006-06-08

申请号：JP2004335819

申请日：2004-11-19

Applicant: Matsushita Electric Works Ltd ,  松下電工株式会社

Inventor： YOSHIHARA TAKAAKI ,  OKA NAOMASA ,  SUZUKI YUJI ,  NOGE HIROSHI

IPC: G02B26/08 ,  B81B3/00 ,  B81B7/04

Abstract: PROBLEM TO BE SOLVED: To provide an optical switch with which miniaturization as the whole device is possible by arranging optical fibers always in two directions in optical input sections 41, 44 and optical output sections 42, 43. SOLUTION: The optical switch comprises: a plurality of movable mirrors R 11 -R NN arranged in a matrix; the optical input sections 41, 44 and optical output sections 42, 43 arranged on the opposing two sides of the matrix respectively; and fixed mirrors 21, 22 arranged on at least one of the other opposing two sides of the matrix and equipped with a reflection area nearly parallel to the diagonal direction of the matrix. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种光开关，通过在光输入部分41,44和光输出部分42,43中总是沿着两个方向布置光纤，可以使整个装置成为小型化。解决方案： 光学开关包括：以矩阵形式布置的多个可移动反射镜R SB7-NNS 分别布置在矩阵的相对两侧的光输入部分41,44和光输出部分42,43; 以及布置在矩阵的另一个相对的两个侧面中的至少一个上并且具有几乎平行于矩阵的对角线方向的反射区域的固定镜21,22。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2006015440A

公开(公告)日：2006-01-19

申请号：JP2004194543

申请日：2004-06-30

Applicant: Matsushita Electric Works Ltd ,  松下電工株式会社

Inventor： YOSHIHARA TAKAAKI ,  OKA NAOMASA ,  OGIWARA ATSUSHI ,  USHIYAMA NAOKI ,  HARADA HIROSHI ,  KONO KIYOHIKO

IPC: B81C1/00 ,  B81B3/00

Abstract: PROBLEM TO BE SOLVED: To easily create a fine three-dimensional structure by suppressing the occurrence of a damaged part by side etching.
SOLUTION: This method of manufacturing a semiconductor structure has a patterning process for selectively eliminating a first substrate 11 from a first main surface of the first substrate 11 to form a plurality of groove parts different in depth; a substrate joining process for joining the first main surface to the main surface of a second substrate; and a back face etching process for uniformly eliminating the first substrate 11 from a second main surface 11b facing the first main surface, to leave only projecting parts 14 between the groove parts. Prior to the back face etching process, a mask forming process is performed to form masks 22a, 22b, 22c on the second main surface 11b facing a part deeper in the groove part depth than the other groove parts.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：通过抑制侧面蚀刻损坏的发生，容易地形成精细的三维结构。 解决方案：这种制造半导体结构的方法具有用于从第一基板11的第一主表面选择性地去除第一基板11以形成多个不同深度的凹槽部分的图案化工艺; 用于将第一主表面连接到第二基板的主表面的基板接合工艺; 以及用于从面向第一主表面的第二主表面11b均匀地去除第一基板11，仅在凹槽部分之间仅留下突出部分14的背面蚀刻工艺。 在背面蚀刻处理之前，进行掩模形成处理，以在第二主表面11b上形成面对凹槽部分深度比其他凹槽部分更深的部分的掩模22a，22b，22c。 版权所有（C）2006，JPO＆NCIPI