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公开(公告)号：FR2546316B1
公开(公告)日：1987-03-20
申请号：FR8407504
申请日：1984-05-15
Applicant: RCA CORP
Inventor： FLING RUSSELL THOMAS , NAIMPALLY SAIPRASAD VASUODEV
Abstract: Symmetrical truncation of two's complement binary numbers is performed by simply discarding the LSB's of positive values and by adding "one" to the truncated negative value when any one of the discarded LSB's is a logical "one" value. Apparatus to perform an N bit truncation includes an incrementer, a two input AND gate and an N-input OR gate.
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公开(公告)号：GB2178624A
公开(公告)日：1987-02-11
申请号：GB8618180
申请日：1986-07-25
Applicant: RCA CORP
Inventor： WILLIS DONALD HENRY , FLING RUSSELL THOMAS , CHRISTOPHER TODD J
Abstract: In memory-based video signal processing systems such as frame recursive filters, for example, system performance is dependent upon critical timing relationships between incoming signals and delayed signals produced from the memory. Video signal from various sources, e.g. VTR's, tend to have jittering time bases that generally have prevented the use of such memory-based processing systems. The jittering signals may be standardized, in sampled data format, by effecting adaptive signal delays responsive to a measure of the relative phase of the sampling clock with respect to horizontal synchronizing pulses. The phase measure is used to control an interpolator which combines successive samples in proportions to develop sample values that should have occurred at the sample times had the signal not been jittering.
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公开(公告)号：AU6050786A
公开(公告)日：1987-02-05
申请号：AU6050786
申请日：1986-07-24
Applicant: RCA CORP
Inventor： FLING RUSSELL THOMAS
Abstract: In a double scanning receiver including a video speed-up memory with read and write clocks locked to multiples of burst, visible artifacts tend to be produced when displaying non-standard video signals (e.g., from a VCR, gme, computer, etc.) due to skew of the memory clock signals with respect to horizontal sync. Skew artifacts are corrected by delaying (in 95;96,98) the output signal of the memory (50) as a direct function of the read clock skew and as an inverse function of the write clock skew. The write clock skew is measured (410-426,Fig.4) for each memory read and write cycle. The read clock skew (in latch 66) for the first memory read cycle corresponds to the write clock skew (in latch 64) measured at the start of the first read cycle. The read clock skew for the second memory read cycle is obtained by adding to the write clock skew measured at the start of the second read cycle a measured half-line period of the video input signal and taking the fractional part of the sum thereof. The integer part of the sum is detected (68) to initiate the start of the second memory read cycle. The difference (96) between the write skew signal (64) and twice (84) the read skew signal (66) determines the delay imparted to the video signal.
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Patent Agency Ranking
公开(公告)号：FI861124A
公开(公告)日：1986-09-26
申请号：FI861124
申请日：1986-03-18
Applicant: RCA CORP
Inventor： FLING RUSSELL THOMAS , CHRISTOPHER TODD J
Abstract: A pix-in-pix display includes a filtering system for processing the video signals which produce the reduced-size image. The filtering system includes an anti-aliasing filter - (210) which reduces the amplitude of the components of the video signals which may cause aliasing distortion when the image is subsampled. However, the filter passes substantial amounts of these components. The filtered video signal is subsampled (212) and applied to a peaking filter (220) which amplifies the band of frequencies containing the aliasing components relative to lower frequency bands to improve the appearance of detailed portions of the reproduced image.
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公开(公告)号：GB2141271B
公开(公告)日：1986-08-13
申请号：GB8411759
申请日：1984-05-09
Applicant: RCA CORP
Inventor： FLING RUSSELL THOMAS , NAIMPALLY SAIPRASAD VASUDEV
Abstract: Symmetrical truncation of two's complement binary numbers is performed by simply discarding the LSB's of positive values and by adding "one" to the truncated negative value when any one of the discarded LSB's is a logical "one" value. Apparatus to perform an N bit truncation includes an incrementer, a two input AND gate and an N-input OR gate.
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公开(公告)号：FR2574240A1
公开(公告)日：1986-06-06
申请号：FR8517728
申请日：1985-11-29
Applicant: RCA CORP
Inventor： CHRISTOPHER TODD J , FLING RUSSELL THOMAS
Abstract: A television receiver/monitor includes a progressive scan processor including memories for time compressing a video input signal and doubling the line rate to reduce visible line structure when the double line-rate signal is displayed. The memories are controlled to provide a video compression factor (2.5:1) greater than the display line rate increase (2:1) to provide a display retrace time (10.8 micro-seconds) substantially equal to the blanking interval (11.0 micro-seconds) of the video input signal thereby decreasing display power losses and horizontal drive requirements.
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公开(公告)号：FI861705A0
公开(公告)日：1986-04-23
申请号：FI861705
申请日：1986-04-23
Applicant: RCA CORP
Inventor： WILLIS DONALD HENRY , FLING RUSSELL THOMAS
Abstract: A speed-up memory converts interlaced RGB input signals to double line-rate (progressive scan) form. A vertical detail signal is derived from the RGB input signals before or after speed-up and a vertical peaking signal is derived from the detail signal. During the first read operation of the speed-up memory both signals are added to the speeded-up signals to effect a preshoot of the resultant signal and during the second speed-up memory read operation only the peaking signal added to affect an overshoot of the resultant signals whereby alternate lines of the converted RGB signals exhibit enhanced vertical detail.
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公开(公告)号：DE3418033A1
公开(公告)日：1984-11-22
申请号：DE3418033
申请日：1984-05-15
Applicant: RCA CORP
Inventor： FLING RUSSELL THOMAS , NAIMPALLY SAIPRASAD VASUDEV
Abstract: Symmetrical truncation of two's complement binary numbers is performed by simply discarding the LSB's of positive values and by adding "one" to the truncated negative value when any one of the discarded LSB's is a logical "one" value. Apparatus to perform an N bit truncation includes an incrementer, a two input AND gate and an N-input OR gate.
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