71.
    发明专利
    未知

    公开(公告)号:DE69821861D1

    公开(公告)日:2004-04-01

    申请号:DE69821861

    申请日:1998-10-20

    Inventor: BELOT DIDIER

    Abstract: The quality factor for the two sets of inductance capacitance circuits is different, allowing the two circuits to be paralleled or for one of the circuits to be placed in the frequency stop band.

    72.
    发明专利
    未知

    公开(公告)号:FR2787636B1

    公开(公告)日:2001-03-16

    申请号:FR9815941

    申请日:1998-12-17

    Inventor: BELOT DIDIER

    Abstract: A built-in circuit includes a semiconductor substrate (SB) with a bottom part (PSB) and upper layer (CSB) strongly doped that the bottom part. A first block (BC3) and a second block (BC1) are formed in the upper part of the substrate. An isolating device is arranged closed to the second block (BC1) and includes an isolating circuit (CRS) linked to the bottom part of the substrate (PSB). A mass connection (PTMD1) provide a minimal impedance at a given frequency.

    75.
    发明专利
    未知

    公开(公告)号:DE69608920D1

    公开(公告)日:2000-07-27

    申请号:DE69608920

    申请日:1996-03-05

    Abstract: An amplifier stage has an MOS load transistor with regulatable load (Rv), a regulatable polarisation current source (Iv), regulated as the frequency of stage function. The transistor is controlled so that the product of polarisation current and the load transistor resistance is constant. The regulation comprises an MOS transistor connected as a diode (Rc) forming a current mirror with the load transistor. A number of constant current control sources (Ic) are selected individually by respective signals (S) to polarise the diode connected transistor. A number of constant current polarisation sources (Iv) form the source of regulatable current, selected to polarise the amplifier stage. The sources of polarisation and control current associated with the same selection signal may constitute two outputs of the same current mirror.

    76.
    发明专利
    未知

    公开(公告)号:FR2787636A1

    公开(公告)日:2000-06-23

    申请号:FR9815941

    申请日:1998-12-17

    Inventor: BELOT DIDIER

    Abstract: A built-in circuit includes a semiconductor substrate (SB) with a bottom part (PSB) and upper layer (CSB) strongly doped that the bottom part. A first block (BC3) and a second block (BC1) are formed in the upper part of the substrate. An isolating device is arranged closed to the second block (BC1) and includes an isolating circuit (CRS) linked to the bottom part of the substrate (PSB). A mass connection (PTMD1) provide a minimal impedance at a given frequency.

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