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71.发明授权公开(公告)号：US10211048B2
公开(公告)日：2019-02-19
申请号：US13756806
申请日：2013-02-01
Applicant: Sensor Electronic Technology, Inc.
Inventor： Wenhong Sun , Rakesh Jain , Jinwei Yang , Maxim S. Shatalov , Alexander Dobrinsky , Remigijus Gaska , Michael Shur
Abstract: A solution for fabricating a semiconductor structure is provided. The semiconductor structure includes a plurality of semiconductor layers grown over a substrate using a set of epitaxial growth periods. During each epitaxial growth period, a first semiconductor layer having one of: a tensile stress or a compressive stress is grown followed by growth of a second semiconductor layer having the other of: the tensile stress or the compressive stress directly on the first semiconductor layer. One or more of a set of growth conditions, a thickness of one or both of the layers, and/or a lattice mismatch between the layers can be configured to create a target level of compressive and/or shear stress within a minimum percentage of the interface between the layers.
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公开(公告)号：US20180323071A1
公开(公告)日：2018-11-08
申请号：US16022939
申请日：2018-06-29
Applicant: Sensor Electronic Technology, Inc.
Inventor： Maxim S. Shatalov , Jinwei Yang , Wenhong Sun , Rakesh Jain , Michael Shur , Remigijus Gaska
Abstract: A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.
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公开(公告)号：US20180269355A1
公开(公告)日：2018-09-20
申请号：US15989275
申请日：2018-05-25
Applicant: Sensor Electronic Technology, Inc.
Inventor： Rakesh Jain , Wenhong Sun , Jinwei Yang , Maxim S. Shatalov , Alexander Dobrinsky , Michael Shur , Remigijus Gaska
IPC: H01L33/12
CPC classification number: H01L33/12 , C30B25/04 , C30B25/183 , C30B29/406 , H01L21/0242 , H01L21/0243 , H01L21/02458 , H01L21/0254 , H01L21/02639 , H01L21/0265 , H01L29/2003 , H01L29/205 , H01L29/518 , H01L29/7786 , H01L29/7787 , H01L33/007 , H01L33/0075 , H01L33/06 , H01L33/10 , H01L33/145 , H01L33/22 , H01L33/24 , H01L33/32 , H01L33/405 , H01L2933/0091
Abstract: A method of fabricating a device using a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions. A device including one or more of these features also is provided.
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公开(公告)号：US10050175B2
公开(公告)日：2018-08-14
申请号：US15797263
申请日：2017-10-30
Applicant: Sensor Electronic Technology, Inc.
Inventor： Rakesh Jain , Wenhong Sun , Jinwei Yang , Maxim S. Shatalov , Alexander Dobrinsky , Michael Shur , Remigijus Gaska
IPC: H01L27/15 , H01L31/072 , H01L33/06 , H01L21/02 , H01L29/778 , H01L33/12 , H01L33/24 , H01L33/32 , H01L29/20 , H01L29/51 , H01L33/22
Abstract: A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.
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公开(公告)号：US09997667B2
公开(公告)日：2018-06-12
申请号：US15495169
申请日：2017-04-24
Applicant: Sensor Electronic Technology, Inc.
Inventor： Maxim S. Shatalov , Remigijus Gaska , Jinwei Yang , Michael Shur , Alexander Dobrinsky
CPC classification number: H01L33/06 , B82Y10/00 , B82Y20/00 , H01L29/15 , H01L29/155 , H01L29/2003 , H01L29/201 , H01L29/207 , H01L33/0075 , H01L33/04 , H01L33/145 , H01L33/32 , H01L33/325 , H01S5/2009 , H01S5/3211 , H01S5/3216 , H01S5/3407 , H01S5/34333
Abstract: A solution for designing and/or fabricating a structure including a quantum well and an adjacent barrier is provided. A target band discontinuity between the quantum well and the adjacent barrier is selected to coincide with an activation energy of a dopant for the quantum well and/or barrier. For example, a target valence band discontinuity can be selected such that a dopant energy level of a dopant in the adjacent barrier coincides with a valence energy band edge for the quantum well and/or a ground state energy for free carriers in a valence energy band for the quantum well. Additionally, a target doping level for the quantum well and/or adjacent barrier can be selected to facilitate a real space transfer of holes across the barrier. The quantum well and the adjacent barrier can be formed such that the actual band discontinuity and/or actual doping level(s) correspond to the relevant target(s).
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Patent Agency Ranking
公开(公告)号：US09911895B2
公开(公告)日：2018-03-06
申请号：US15069178
申请日：2016-03-14
Applicant: Sensor Electronic Technology, Inc.
Inventor： Maxim S. Shatalov , Alexander Dobrinsky , Alexander Lunev , Rakesh Jain , Jinwei Yang , Michael Shur , Remigijus Gaska
CPC classification number: H01L33/0025 , H01L33/0075 , H01L33/10 , H01L33/32 , H01L33/46 , H01S5/0224
Abstract: A semiconductor layer including a plurality of inhomogeneous regions is provided. Each inhomogeneous region has one or more attributes that differ from a material forming the semiconductor layer. The inhomogeneous regions can include one or more regions configured based on radiation having a target wavelength. These regions can include transparent and/or reflective regions. The inhomogeneous regions also can include one or more regions having a higher conductivity than a conductivity of the radiation-based regions, e.g., at least ten percent higher.
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公开(公告)号：US20180047870A1
公开(公告)日：2018-02-15
申请号：US15797263
申请日：2017-10-30
Applicant: Sensor Electronic Technology, Inc.
Inventor： Rakesh Jain , Wenhong Sun , Jinwei Yang , Maxim S. Shatalov , Alexander Dobrinsky , Michael Shur , Remigijus Gaska
IPC: H01L33/06 , H01L33/12 , H01L29/778 , H01L33/24 , H01L21/02 , H01L33/32 , H01L33/22 , H01L29/20 , H01L29/51
CPC classification number: H01L33/06 , H01L21/0242 , H01L21/0243 , H01L21/02458 , H01L21/0254 , H01L21/02639 , H01L21/0265 , H01L29/2003 , H01L29/518 , H01L29/7786 , H01L33/12 , H01L33/22 , H01L33/24 , H01L33/32 , H01L2933/0083 , H01L2933/0091
Abstract: A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.
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公开(公告)号：US20170345968A1
公开(公告)日：2017-11-30
申请号：US15662675
申请日：2017-07-28
Applicant: Sensor Electronic Technology, Inc.
Inventor： Wenhong Sun , Alexander Dobrinsky , Maxim S. Shatalov , Jinwei Yang , Michael Shur , Remigijus Gaska
CPC classification number: H01L33/06 , H01L21/02389 , H01L21/02505 , H01L21/02507 , H01L21/02513 , H01L33/0066 , H01L33/0075 , H01L33/04
Abstract: A light emitting heterostructure including one or more fine structure regions is provided. The light emitting heterostructure can include a plurality of barriers alternating with a plurality of quantum wells. One or more of the barriers and/or quantum wells includes a fine structure region. The fine structure region includes a plurality of subscale features arranged in at least one of: a growth or a lateral direction.
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公开(公告)号：US20170287698A1
公开(公告)日：2017-10-05
申请号：US15633141
申请日：2017-06-26
Applicant: Sensor Electronic Technology, Inc.
Inventor： Rakesh Jain , Wenhong Sun , Jinwei Yang , Maxim S. Shatalov , Alexander Dobrinsky , Michael Shur , Remigijus Gaska
IPC: H01L21/02 , H01L33/12 , H01L33/32 , H01L33/14 , H01L33/06 , C30B25/04 , H01L33/10 , H01L29/778 , H01L29/20 , H01L29/205 , C30B29/40 , C30B25/18 , H01L33/22 , H01L33/40
CPC classification number: H01L33/12 , C30B25/04 , C30B25/183 , C30B29/406 , H01L21/0242 , H01L21/0243 , H01L21/02458 , H01L21/0254 , H01L21/02639 , H01L21/0265 , H01L29/2003 , H01L29/205 , H01L29/518 , H01L29/7786 , H01L29/7787 , H01L33/06 , H01L33/10 , H01L33/145 , H01L33/22 , H01L33/24 , H01L33/32 , H01L33/405 , H01L2933/0091
Abstract: A method of fabricating a device using a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-Ill nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions. A device including one or more of these features also is provided.
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公开(公告)号：US20170229610A1
公开(公告)日：2017-08-10
申请号：US15495169
申请日：2017-04-24
Applicant: Sensor Electronic Technology, Inc.
Inventor： Maxim S. Shatalov , Remigijus Gaska , Jinwei Yang , Michael Shur , Alexander Dobrinsky
CPC classification number: H01L33/06 , B82Y10/00 , B82Y20/00 , H01L29/15 , H01L29/155 , H01L29/2003 , H01L29/201 , H01L29/207 , H01L33/0075 , H01L33/04 , H01L33/145 , H01L33/32 , H01L33/325 , H01S5/2009 , H01S5/3211 , H01S5/3216 , H01S5/3407 , H01S5/34333
Abstract: A solution for designing and/or fabricating a structure including a quantum well and an adjacent barrier is provided. A target band discontinuity between the quantum well and the adjacent barrier is selected to coincide with an activation energy of a dopant for the quantum well and/or barrier. For example, a target valence band discontinuity can be selected such that a dopant energy level of a dopant in the adjacent barrier coincides with a valence energy band edge for the quantum well and/or a ground state energy for free carriers in a valence energy band for the quantum well. Additionally, a target doping level for the quantum well and/or adjacent barrier can be selected to facilitate a real space transfer of holes across the barrier. The quantum well and the adjacent barrier can be formed such that the actual band discontinuity and/or actual doping level(s) correspond to the relevant target(s).
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