公开(公告)号：JP2004111875A

公开(公告)日：2004-04-08

申请号：JP2002276090

申请日：2002-09-20

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： NOJIMA SHIGEKI ,  SANHONGI SHOJI ,  HASEBE SHIGERU ,  HASHIMOTO KOJI ,  INOUE SOICHI ,  IKEDA TAKAHIRO

IPC: G03F7/20 ,  G03F1/36 ,  G03F1/68 ,  G03F1/70 ,  H01L21/00 ,  H01L21/02 ,  H01L21/027 ,  H01L21/82

Abstract: PROBLEM TO BE SOLVED: To provide an information providing system relating to the manufacture of an integrated circuit device capable of selecting optimum manufacturing method when a shape on a wafer differs from design data. SOLUTION: A consultant side 13 receives design data of a target circuit pattern of an integrated circuit device, a difference between a pattern form formed on a substrate using the design data and the design data, and manufacturing process information when the circuit pattern is formed on the substrate from a manufacturer side 11 via a network 12. The consultant side 13 derives a means for reducing the difference on the basis of the design data, the difference, and the manufacturing process information, and calculates the cost and time required for the derived means and a reduction effect for a manufacturing cost obtained by reducing the difference. Further, the consultant side 13 provides the means for reducing the difference, the cost and time and the effect of manufacturing cost reduction to the manufacturer side 11 via the network 12. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2004101654A

公开(公告)日：2004-04-02

申请号：JP2002260428

申请日：2002-09-05

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： YAMAGUCHI SHINJI ,  TANAKA SATOSHI ,  INOUE SOICHI

IPC: G01N21/956 ,  G03F1/84 ,  G03F7/20 ,  G06T1/00 ,  H01L21/027 ,  H01L21/66 ,  G03F1/08

Abstract: PROBLEM TO BE SOLVED: To provide an inspection method of mask defects for shortening the manufacturing period of a photomask. SOLUTION: A map of influential degrees of defects is prepared, the map including detection sensitivity K-N of defects in each of a plurality of positions in a cell pattern region determined according to the influential degree of defects in the respective position on a wafer. Then defects in the plurality of positions in the cell pattern region are inspected by adopting the inspection sensitivity K-N in the map of influential degrees of defects. COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：提供掩模缺陷的检查方法，以缩短光掩模的制造周期。 解决方案：制作出有影响程度的缺陷图，该图包括根据晶片上各个位置的有害程度影响确定的单元格图案区域中的多个位置中的每一个中的缺陷的检测灵敏度KN 。 然后通过在有影响的缺陷度图中采用检测灵敏度K-N来检查单元图案区域中的多个位置中的缺陷。 版权所有（C）2004，JPO

公开(公告)号：JP2004030579A

公开(公告)日：2004-01-29

申请号：JP2003064592

申请日：2003-03-11

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： KOTANI TOSHIYA ,  TANAKA SATOSHI ,  INOUE SOICHI ,  MORI ICHIRO ,  HASHIMOTO KOJI

IPC: G06F17/50 ,  H01L21/82

Abstract: PROBLEM TO BE SOLVED: To provide a method and a system which simultaneously decide optimal design rules and the optimal process parameters while reducing the chip area.
SOLUTION: A design rule (D.R,)/process parameter (P.P) decision system 2 is provided with a compaction means 8 which compacts design layout data based on a D.R. table, a chip size information acquisition means 10 which calculates chip size information of the compacted layout data, a shape information acquisition means 14 which predicts the finished shape of the compacted layout on a wafer according to the P.P, a comparison means 16 which compares the predicted finished shape with the compacted layout, a dangerous pattern information acquisition means 18 which extracts a dangerous pattern from the compacted layout based on a comparison result and a decision means 20 which decides at least one of the D.R. and the P.P. so that both of the chip size and the dangerous pattern satisfy prescribed evaluation conditions.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2003257834A

公开(公告)日：2003-09-12

申请号：JP2002057758

申请日：2002-03-04

Applicant: TOSHIBA CORP

Inventor： ITO SHINICHI ,  TOUKI TATSUHIKO ,  OKUMURA KATSUYA ,  KAWANO KENJI ,  INOUE SOICHI

IPC: G03F7/207 ,  G03F7/20 ,  G03F9/00 ,  H01L21/02 ,  H01L21/027

Abstract: PROBLEM TO BE SOLVED: To provide an exposure method of restraining semiconductor devices from increasing in rejection rate without reworking based on an inspection result that misalignment is detected in lithography. SOLUTION: A photosensitive film is formed on a main surface of a semiconductor substrate (S101), the semiconductor substrate is transferred to an aligner (S102), image of an inspection mark on a mask is selectively projected onto the photosensitive film for exposure to form a latent image of the inspection mark on the photosensitive film (S105), a region of the photosensitive film where the latent image of the inspection mark is formed is heated to reveal the image of a second inspection mark (S106), revealed image of the inspection mark is measured (S107), the set value of the aligner at selective exposure is changed so as to make exposure conditions equal to design values corresponding to the measurement result (S109), the image of a device pattern on the mask is projected onto the photosensitive film for exposure based on the changed set value to form the latent image of the device pattern on the photosensitive film (S110), all the photosensitive film is heated (S111), and the photosensitive film is developed (S112). COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2003107664A

公开(公告)日：2003-04-09

申请号：JP2001375025

申请日：2001-09-29

Applicant: TOSHIBA CORP

Inventor： KOTANI TOSHIYA ,  TANAKA SATOSHI ,  INOUE SOICHI ,  KOBAYASHI SACHIKO

IPC: G03F1/36 ,  G03F1/68 ,  G03F1/70 ,  G03F7/20 ,  G06F17/50 ,  H01L21/027 ,  H01L21/82 ,  G03F1/08

Abstract: PROBLEM TO BE SOLVED: To improve TAT (turn around time) in the formation of a mask pattern. SOLUTION: A compensation value library in which a group of edge coordinates of the pattern and a group of edge coordinates corresponding to them are registered is created (S102) by completion of design of a design pattern, a group of edge coordinates of a pattern of an area centering around a reference point set in the deign pattern after the completion of design are calculated (S104), the compensation value library is referred about the group of edge coordinates (S107), when the group of edge coordinates are unregistered in the compensation value library, a compensation value is calculated (S110) by simulation based on a compensation parameter predetermined to the group of edge coordinates, the calculated compensation value and the group of edge coordinates corresponding to it are additionally registered in the compensation value library (S111), when the group of edge coordinates are already registered in the compensation value library, the compensation value stored in the compensation value library is read (S108) and the mask pattern is generated (S109) by compensating the design pattern according to the compensation value.

公开(公告)号：JP2002341514A

公开(公告)日：2002-11-27

申请号：JP2001145253

申请日：2001-05-15

Applicant: TOSHIBA CORP

Inventor： KOTANI TOSHIYA ,  TANAKA SATOSHI ,  INOUE SOICHI

IPC: G03F1/36 ,  G03F1/68 ,  G03F1/70 ,  G06F17/50 ,  H01L21/027 ,  G03F1/08

Abstract: PROBLEM TO BE SOLVED: To provide a mask data generation method for compatibly improving correction accuracy and shortening correction time. SOLUTION: Instead of correcting a plurality of patterns stipulated by design data by using a single common correction parameter, the plurality of the patterns are classified into a plurality of layers (step S3), an appropriate correction parameter is allocated to each layer (step S4), then each layer is corrected by using the correction parameter allocated to it and a plurality of corrected layers are prepared (step S5). Then, the corrected layers are combined to obtain mask data (step S6).

公开(公告)号：JP2002328460A

公开(公告)日：2002-11-15

申请号：JP2001130969

申请日：2001-04-27

Applicant: TOSHIBA CORP

Inventor： KOTANI TOSHIYA ,  TANAKA SATOSHI ,  INOUE SOICHI

IPC: G03F1/36 ,  G03F1/68 ,  G03F7/20 ,  H01L21/027 ,  G03F1/08

Abstract: PROBLEM TO BE SOLVED: To obtain an exposure mask, a method for manufacturing the mask and a method for forming a pattern so that a cell can be finished to its most end part in a desired dimension without using a dummy pattern, therefore, without increasing the cell area. SOLUTION: The end part of the memory cell is subjected to optical proximity correction/process proximity correction(PPC) so as to decrease the dimensional difference in the finished pattern in the end region of the memory cell. By subjecting the end part of the memory cell to the PPC, the cell can be finished to the most end part of the cell into a desired dimension without increasing the cell area. Since the mask dimension of the end part of the cell can be determined by the PPC, the designer is not required to change the design of the cell end even when the conditions for the lithographic process are changed. That is, the optimum mask dimension of the cell end can be obtained only by changing the rule of the PPC according to the changes in the lithographic process, and this results in the decrease in the load relating to designing.

公开(公告)号：JP2001351853A

公开(公告)日：2001-12-21

申请号：JP2000172625

申请日：2000-06-08

Applicant: TOSHIBA CORP

Inventor： DEWA KYOKO ,  INOUE SOICHI

IPC: G01B11/00 ,  G01B11/02 ,  G02B7/28 ,  G03F7/207 ,  H01L21/027

Abstract: PROBLEM TO BE SOLVED: To precisely simply detect displacement and direction thereof from focused state and contribute for improvement of exposure accuracy and the like. SOLUTION: The displacement from optimum focused state is monitored on the occasion of pattern transcription on a wafer 115 in an aligner 110 provided by a focus measuring device 130 for measuring the height position of the wafer surface with diagonal incident illumination with a focus monitor method. The displacement and direction thereof from the focused position are acquired by transferring a pattern on the wafer 115 by use of a mask 113 having a focus monitor pattern with its dimension changed according to the displacement from focus state, acquiring position information by the focus measuring device 130 on the occasion of pattern transferring, and measuring the pattern dimension of the focus monitor pattern projected on the wafer 115 with the measuring device 120 to obtain the displacement and direction thereof from focused position according to the acquired information on the position and the pattern dimension measured.

公开(公告)号：JP2000269119A

公开(公告)日：2000-09-29

申请号：JP7349499

申请日：1999-03-18

Applicant: TOSHIBA CORP

Inventor： SATO KAZUYA ,  INOUE SOICHI

IPC: H01L21/027 ,  G03F7/20

Abstract: PROBLEM TO BE SOLVED: To simply measure numerical aperture NA on the wafer side in an aligner. SOLUTION: A method for measuring NA of an aligner, which measures an actual numerical aperture NA on the wafer side of a projection optical system in an aligner, in which the light emitted from a light source is introduced to an optical part by an illumination optical system, and the optical image of the optical part is focused on a wafer by an projection optical system. An optical part is placed on a reticle plane, and patterns thereon are exposed on a wafer, wherein the patterns contain a plurality of basic patterns, each having at least two periods or more of a line-and-space pattern consisting of a shielding part 1 and a translucent part 2, arranged at least in one direction on the optical part, and the periods of the patterns contain periods p1 and p2 satisfying p1

公开(公告)号：JP2000098584A

公开(公告)日：2000-04-07

申请号：JP14037799

申请日：1999-05-20

Applicant: TOSHIBA CORP

Inventor： KOTANI TOSHIYA ,  TANAKA SATOSHI ,  INOUE SOICHI

IPC: H01L21/027 ,  G03F1/36 ,  G03F1/68 ,  G03F1/70 ,  G03F7/20 ,  G06F17/50 ,  G03F1/08

Abstract: PROBLEM TO BE SOLVED: To optimize the amount of movement of a pattern edge position with high accuracy in a short time by performing fewer numbers of calculation times. SOLUTION: This method is for preparing a second mask pattern 2 in which the whole edge positions constituting a first mask pattern 1 is moved by a prescribed amount of change, for obtaining a first finish planar shape to be transferred with the first mask pattern 1 and a second finish planar shape to be transferred with the second mask pattern 2 by calculation, for calculating a coefficient in which the dimension of the difference between each of pattern edge positions of the first and second finish planar shapes is divided by the changing amt. and assigning the calculated coefficient for every edge and for preparing a correction pattern in which the edge positions of the first mask pattern 1 are moved for every edge by the magnitude in which the dimension of the difference between a designed pattern and the first finish planar shape is divided by the coefficient assigned for every edge.