-
公开(公告)号：GB2472701A
公开(公告)日：2011-02-16
申请号：GB201014826
申请日：2006-12-22
Applicant: WOLFSON MICROELECTRONICS PLC
Inventor： LESSO JOHN PAUL , PENNOCK JOHN LAURENCE , FRITH PETER JOHN
IPC: H02M3/07
Abstract: Disclosed is a dual mode charge-pump circuit for providing a plurality of output voltages Vout+, Vout-, using a single flying capacitor Cf. The circuit comprises a network of switches 410 that is operable in a number of different states and a controller 420 for operating the switches 410 in a sequence of states so as to generate positive and negative output voltages together spanning a voltage approximately equal to the input voltage +Vdd and centred on the voltage at the common terminal. The circuit may also be operated so as to generate positive and negative output voltages each up to substantially the input voltage.
-
公开(公告)号：GB2466521A
公开(公告)日：2010-06-30
申请号：GB0823614
申请日：2008-12-29
Applicant: WOLFSON MICROELECTRONICS PLC
Inventor： LESSO JOHN PAUL
IPC: H03L7/081
Abstract: A frequency generation circuit comprises an input for receiving a signal at a first frequency F1, a divider 14 for producing a second, intermediate frequency F2, and a delay locked loop circuit 16 which receives the intermediate signal and generates an output signal by multiplying the intermediate signal by a multiplication ratio. The division ratio of the divider and the multiplication ratio of the delay locked loop are co-prime. The delay locked loop circuit 16 includes a voltage controlled delay line 22, which may employ an edge combiner (40, fig. 2) or a phase interpolator (60, fig.3) to produce the output signal from the cells of the delay line. The delay line introduces a delay that is made to be equal to one period of the clock signal at the intermediate frequency F2. The arrangement provides a frequency multiplication circuit based around a delay locked loop, but which allows non-integer multiplication ratios to be achieved.
-
公开(公告)号：GB2459862B
公开(公告)日：2010-06-30
申请号：GB0808292
申请日：2008-05-07
Applicant: WOLFSON MICROELECTRONICS PLC
Inventor： STEELE COLIN FINDLAY , STOJANOVIC GORAN , LESSO JOHN PAUL
-
公开(公告)号：GB2459865A
公开(公告)日：2009-11-11
申请号：GB0808297
申请日：2008-05-07
Applicant: WOLFSON MICROELECTRONICS PLC
Inventor： LESSO JOHN PAUL
Abstract: An audio amplifier circuit with dc offset compensation is disclosed. The circuit includes an amplifier 205 and a digital feedback circuit 245 including an ADC 215 and a DAC 235. The feedback loop also includes a low pass filter 220, a comparator 225 and an integrator 230. Once the output from the integrator 230 has reached a stable value to compensate for any dc offset, the output can be latched and continuously combined with the input signal via the ADC 235 and the summing element 240. The components in the digital feedback circuit may be multiplexed to serve more than one audio channel (fig.5). The circuit may be used to reduce 'pop' or 'plop' when an audio amplifier is switched on or off. Such noises are irritating to a user and also represent wasted power, which is important in battery powered portable audio players. The system may also be used to remove do offset from an input signal to an audio integrated circuit, thereby minimising pin count on the integrated circuit as no external do blocking capacitor is required.
-
公开(公告)号：GB2452271A
公开(公告)日：2009-03-04
申请号：GB0716715
申请日：2007-08-29
Applicant: WOLFSON MICROELECTRONICS PLC
Inventor： LESSO JOHN PAUL , JOHNSON DAVID EDWIN
Abstract: The invention reduces pin count by a method of using time division multiplexing (TDM) techniques to enable a plurality of functions of an integrated circuit to be controlled on a single pin of said circuit. The method involves providing each function with a designated periodically recurring sampling instance, e.g. a timeslot, during which time the status of a signal on the single pin will relate to the function designated to that timeslot, and controlling each of the functions according to the status of signal during their corresponding timeslots. The invention may be applied to stereo audio digital-to-analogue conversion (DAC) circuitry or ADCs. For example, mute and de-emphasis functions may be controlled on a single pin MUTE_DEEM by de-multiplexing a combined mute/de-emphasis signal using two D-type flip-flops 400, 410, inverter 420 and left-right clock signal LRCK. The invention may also allow for zero detection (ZD) to be used on the combined MUTE_DEEM pin.
-
Patent Agency Ranking
公开(公告)号：GB2451525A
公开(公告)日：2009-02-04
申请号：GB0716919
申请日：2007-08-30
Applicant: WOLFSON MICROELECTRONICS PLC
Inventor： LESSO JOHN PAUL
Abstract: A power amplifier 106 is supplied with voltage by a switching power supply 304 whose switching frequency varies with a volume setting signal to a pre-amplifier 118. The switching frequency is determined by clock generator 306 and may also depend on the variable gain of preamplifier 118, and on the input signal, detected by an envelope detector 302. Switching power supply 304 may be a level-shifting charge pump (fig 14a) comprising a flying capacitor (fig 14a, Cf) a network of switches (fig 14a, S1-S6) and reservoir capacitors 108,110 and that can supply plural voltages to the power amplifier. When the volume is large the reservoir capacitors will discharge rapidly so an increased switching frequency can maintain their voltage at an adequate level. The circuit may implemented as an integrated circuit such as an ASIC or FPGA using suitable control code. It may be used as part of an audio or video system such as an MP3 player, a mobile phone, camera or navigation system and may be battery or mains powered.
-
公开(公告)号：GB2451473A
公开(公告)日：2009-02-04
申请号：GB0714888
申请日：2007-07-31
Applicant: WOLFSON MICROELECTRONICS PLC
Inventor： LESSO JOHN PAUL , PENNOCK JOHN LAURENCE
IPC: H03L7/197
Abstract: The present invention relates to dithering or modulating a clock signal to spread its spectrum. The invention (fig.5) provides an input (fref) for receiving a clock signal having a first frequency; a divider (50), for generating an output signal having an instantaneous frequency equal to the first frequency divided by an instantaneous division ratio; and a sequence generator (60, 70, 80), for generating a sequence of instantaneous division ratios by adding a sequence of instantaneous dither values to an integer value. The instantaneous division ratios in said sequence have a mean value that is equal to an integer desired ratio, but none of the instantaneous division ratios in said sequence is equal to the integer desired ratio. A variant (fig.6) is also disclosed in which the clock frequency is synthesized using a fractional division. The system may be used to provide a dithered clock signal for dc-dc converters in audio or video systems.
-
公开(公告)号：GB2447426A
公开(公告)日：2008-09-17
申请号：GB0625957
申请日：2006-12-22
Applicant: WOLFSON MICROELECTRONICS PLC
Inventor： LESSO JOHN PAUL , PENNOCK JOHN , FRITH PETER JOHN
Abstract: A charge pump circuit uses a single flying capacitor to supply dual-rail positive and negative output voltages from a single input voltage. The circuit comprises a controller 420 that opens and closes a network of switches S1-S6 in sequence, connecting an input voltage VDD, either directly or via a flying capacitor Cfb, to transfer packets of charge to reservoir capacitors CR1,CR2, to generate bipolar output voltages Vout+,Vout- which together span a voltage equal to the input voltage +VDD, and are centred on a common terminal N11. The sequence of switching may include overlapping states, interleaving states, repeating states, and states whereby the flying capacitor voltage is divided between the two output voltages. The sequence of switch states can be varied depending on load conditions, and the output voltages can be regulated depending on comparison with thresholds (fig 9). The charge pump may be used to supply audio (fig 11a), stereo (fig 11b), headphone, communication or in-car apparatus.
-
公开(公告)号：CA2711022C
公开(公告)日：2016-05-10
申请号：CA2711022
申请日：2008-08-04
Applicant: WOLFSON MICROELECTRONICS PLC
Inventor： LESSO JOHN PAUL
IPC: H03F1/02
Abstract: An amplifier circuit comprises an input, for receiving an input signal to be amplified; a preamplifier, for amplifying the input signal based on a variable gain; a power amplifier for amplifying the signal output from the preamplifier; and a variable voltage power supply for supplying one or more supply voltages to the power amplifier. The supply voltages are adjusted based on the variable gain or the input digital signal. According to other aspects of the invention, a power supply of an amplifier circuit is clocked using a clock signal, whereby the clock signal has a frequency that varies in accordance with a volume signal or an input signal.
-
公开(公告)号：GB2502557A
公开(公告)日：2013-12-04
申请号：GB201209600
申请日：2012-05-30
Applicant: WOLFSON MICROELECTRONICS PLC
Inventor： LESSO JOHN PAUL , PENNOCK JOHN LAURENCE
Abstract: Analogue-to-digital converters based on voltage-to-frequency conversion are susceptible to gain changes due to manufacturing and thermal variations in the controlled oscillators. In a differential ADC of this type the digital output signal Dout is derived from the difference in pulse rates from the two signal-controlled oscillators 202,203. A further pulse count Cout independent of the differential input signal, such as a sum or average of the pulse rates from the two oscillators, may be used to derive a regulating signal SFB for controlling the gain of the VCO/ CCO pair or the clocked integration period (figure 24) of the counters in block 204. Alternatively the digital output may be scaled by the regulating signal (SFF, figure 25). Clipping due to signal overload may be overcome by reducing the gain of the VCO/CCO pair when the input signals are excessive (figures 29-31).
-
-
-
-
-
-
-
-
-
Search Results
98
records
(took 0.065 seconds)
