公开(公告)号：US12089409B2

公开(公告)日：2024-09-10

申请号：US18339526

申请日：2023-06-22

Applicant: KIOXIA CORPORATION

Inventor： Masayoshi Tagami ,  Jun Iijima ,  Ryota Katsumata ,  Kazuyuki Higashi

IPC: H01L23/522 ,  H01L23/00 ,  H01L25/065 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  G11C5/02 ,  G11C16/04 ,  G11C16/26

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H01L24/04 ,  H01L25/0657 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  G11C5/02 ,  G11C16/0483 ,  G11C16/26 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/05095 ,  H01L2224/05569 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/08146 ,  H01L2224/80201 ,  H01L2224/80894 ,  H01L2224/80895 ,  H01L2924/1304 ,  H01L2924/13091 ,  H01L2924/1434 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2924/1434 ,  H01L2924/00012 ,  H01L2924/13091 ,  H01L2924/00012 ,  H01L2924/1304 ,  H01L2924/00012 ,  H01L2224/05647 ,  H01L2924/00014

Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.

公开(公告)号：US20240222313A1

公开(公告)日：2024-07-04

申请号：US18089732

申请日：2022-12-28

Applicant: International Business Machines Corporation

Inventor： Roy R. Yu ,  Katsuyuki Sakuma

IPC: H01L23/00 ,  H01L21/683 ,  H01L21/78

CPC classification number: H01L24/80 ,  H01L21/6838 ,  H01L21/78 ,  H01L2224/80011 ,  H01L2224/80013 ,  H01L2224/80019 ,  H01L2224/80201 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80948

Abstract: An apparatus for bonding a first substrate to a second substrate includes a heatable mounting stage configured to accommodate a first semiconductor substrate on an upward-facing surface and a first stack of semiconductor materials on the first semiconductor substrate; a heatable bond head configured to accommodate a second semiconductor substrate on a downward-facing surface and a second stack of semiconductor materials on the second semiconductor substrate; and a collet disposed on the downward-facing surface of the heatable bond head and configured to receive the second semiconductor substrate and the second stack of semiconductor materials. The heatable bond head is configured to have a vacuum applied thereto to deformably accommodate the second semiconductor substrate and the second stack of semiconductor materials against the collet. The heatable bond head is configured to be pressed against the heatable mounting stage to bond the semiconductor materials.

公开(公告)号：US20240090239A1

公开(公告)日：2024-03-14

申请号：US18176557

申请日：2023-03-01

Applicant: Kioxia Corporation

Inventor： Kiichi TACHI ,  Ryota NIHEI ,  Yoshikazu HOSOMURA

IPC: H10B80/00 ,  H01L23/00 ,  H01L23/50

CPC classification number: H10B80/00 ,  H01L23/50 ,  H01L24/05 ,  H01L24/08 ,  H01L24/48 ,  H01L24/80 ,  H01L24/06 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/48463 ,  H01L2224/80201 ,  H01L2224/80357 ,  H01L2224/80379 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/05442 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor device includes a metal layer disposed above a transistor on a first substrate. The metal layer includes a first region extending in a first direction and a second region that has a width in the first direction smaller than the first region and protrudes from the first region in a second direction, and has a first corner portion having an angle larger than 180° as viewed in a third direction between a proximal end portion of the second region and the first region. The metal layer includes a first portion that is disposed within the first region and has a lower surface at a first height, and a second portion that is disposed within the second region and has a lower surface at a second height lower than the first height. A step present at a boundary between the first portion and the second portion is disposed away from an edge of the second region at a first position near the first corner portion in the second direction and adjacent to the edge of the second region at a second position away from the first corner portion than the first position.

公开(公告)号：US20240072004A1

公开(公告)日：2024-02-29

申请号：US18237259

申请日：2023-08-23

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/80 ,  H01L28/60 ,  H01L25/18 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/08145 ,  H01L2224/80201 ,  H01L2224/80357 ,  H01L2224/80379 ,  H01L2224/80896 ,  H01L2924/04642 ,  H01L2924/0504 ,  H01L2924/0544 ,  H01L2924/059

Abstract: A semiconductor assembly is described that includes two semiconductor dies. The first semiconductor die includes a first layer of dielectric material at which a first portion of conductive material implementing a first portion of a passive circuit component is at least partially disposed. The second semiconductor die includes a second layer of dielectric material at which a second portion of conductive material implementing a second portion of the passive circuit component is at least partially disposed. A first contact pad at the first layer of dielectric material and a second contact pad at a second layer of dielectric material are coupled to create an interconnect electrically coupling the first semiconductor die and the second semiconductor die. A metal-metal bond is formed between the first portion of the passive circuit component and the second portion of the passive circuit component to create the passive circuit component.

公开(公告)号：US20230197672A1

公开(公告)日：2023-06-22

申请号：US17930988

申请日：2022-09-09

Applicant: Kioxia Corporation

Inventor： Ai MORI ,  Hiroaki ASHIDATE

IPC: H01L23/00

CPC classification number: H01L24/80 ,  H01L24/74 ,  H01L2224/74 ,  H01L2224/80201 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80908

Abstract: In one embodiment, a semiconductor manufacturing apparatus includes a magnification difference acquirer configured to acquire a value of difference in magnification between a first substrate and a second substrate. The apparatus further includes a deformation amount determiner configured to determine a value of deformation amount of a chuck that holds the first or second substrate, based on the value of the difference in magnification. The apparatus further includes a gap determiner configured to determine a value of a gap between the first substrate and the second substrate, based on the value of the deformation amount. The apparatus further includes a bonding controller configured to control the deformation amount to the determined value and control the gap to the determined value, before the first substrate and the second substrate are bonded together.

公开(公告)号：US20170243853A1

公开(公告)日：2017-08-24

申请号：US15589513

申请日：2017-05-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Xin-Hua Huang ,  Xiaomeng Chen ,  Ping-Yin Liu ,  Lan-Lin Chao

IPC: H01L23/00 ,  H01L21/67 ,  H01L21/68

CPC classification number: H01L24/94 ,  H01L21/67092 ,  H01L21/681 ,  H01L24/08 ,  H01L24/74 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/74 ,  H01L2224/7501 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/753 ,  H01L2224/75702 ,  H01L2224/75744 ,  H01L2224/75745 ,  H01L2224/75802 ,  H01L2224/75804 ,  H01L2224/75822 ,  H01L2224/75824 ,  H01L2224/759 ,  H01L2224/80011 ,  H01L2224/80013 ,  H01L2224/80019 ,  H01L2224/8013 ,  H01L2224/80132 ,  H01L2224/80201 ,  H01L2224/80203 ,  H01L2224/80986 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/80 ,  H01L2924/00015 ,  H01L2224/80121 ,  H01L2924/00

Abstract: Alignment systems, and wafer bonding alignment systems and methods are disclosed. In some embodiments, an alignment system for a wafer bonding system includes means for monitoring an alignment of a first wafer and a second wafer, and means for adjusting a position of the second wafer. The alignment system includes means for feeding back a relative position of the first wafer and the second wafer to the means for adjusting the position of the second wafer before and during a bonding process for the first wafer and the second wafer.

公开(公告)号：US09741595B2

公开(公告)日：2017-08-22

申请号：US14950281

申请日：2015-11-24

Applicant: TOKYO ELECTRON LIMITED

Inventor： Kenji Sugakawa ,  Yuji Mimura ,  Shuhei Matsumoto ,  Takahiro Masunaga ,  Makoto Tsukishima

IPC: H01L21/67 ,  H01L21/66 ,  H01L23/00 ,  H01L21/68 ,  H01L21/822

CPC classification number: H01L21/67248 ,  H01L21/67092 ,  H01L21/681 ,  H01L21/8221 ,  H01L22/12 ,  H01L22/20 ,  H01L24/08 ,  H01L24/75 ,  H01L24/80 ,  H01L24/94 ,  H01L2224/08145 ,  H01L2224/7501 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/75301 ,  H01L2224/75601 ,  H01L2224/7565 ,  H01L2224/75702 ,  H01L2224/75704 ,  H01L2224/75705 ,  H01L2224/75744 ,  H01L2224/75745 ,  H01L2224/75753 ,  H01L2224/75802 ,  H01L2224/75804 ,  H01L2224/75822 ,  H01L2224/75823 ,  H01L2224/75824 ,  H01L2224/759 ,  H01L2224/75981 ,  H01L2224/80003 ,  H01L2224/80013 ,  H01L2224/80048 ,  H01L2224/8013 ,  H01L2224/80132 ,  H01L2224/80201 ,  H01L2224/80894 ,  H01L2224/80908 ,  H01L2224/83201 ,  H01L2224/94 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/80 ,  H01L2924/00014

Abstract: There is provided a method of bonding substrates to each other, which includes: holding a first substrate on a lower surface of a first holding part; adjusting a temperature of a second substrate by a temperature adjusting part to become higher than a temperature of the first substrate; holding the second substrate on an upper surface of a second holding part; inspecting a state of the second substrate by imaging a plurality of reference points of the second substrate with a first imaging part, measuring positions of the reference points, and comparing a measurement result with a predetermined permissible range; and pressing a central portion of the first substrate with a pressing member, bringing the central portion of the first substrate into contact with a central portion of the second substrate, and sequentially bonding the first substrate and the second substrate.

公开(公告)号：US20170140955A1

公开(公告)日：2017-05-18

申请号：US15418413

申请日：2017-01-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ping-Yin Liu ,  Yen-Chang Chu ,  Xin-Hua Huang ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Ru-Liang Lee

IPC: H01L21/67 ,  H01L25/00 ,  H01L21/683

CPC classification number: H01L21/67092 ,  B23B31/305 ,  B23B31/307 ,  H01L21/6838 ,  H01L24/75 ,  H01L24/80 ,  H01L24/94 ,  H01L25/50 ,  H01L2224/7501 ,  H01L2224/75744 ,  H01L2224/75745 ,  H01L2224/75753 ,  H01L2224/80013 ,  H01L2224/8013 ,  H01L2224/80201 ,  H01L2224/80894 ,  H01L2224/94 ,  H01L2225/06593 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/3511 ,  Y10T156/14 ,  H01L2224/80 ,  H01L2224/80001

Abstract: A method includes placing a first wafer onto a surface of a first wafer chuck, the first wafer chuck including multiple first profile control zones separated by one or more shared flexible membranes. The method also includes setting a first profile of the surface of the first wafer chuck. Setting a first profile of the surface of the first wafer chuck includes adjusting a first volume of a first profile control zone of the multiple first profile control zones. Setting a first profile of the surface of the first wafer chuck also includes adjusting a second volume of a second profile control zone of the multiple first profile control zones, the first volume of the first profile control zone being adjusted independently from the second volume of the second profile control zone, and the second adjustable volume encircling the first adjustable volume.

公开(公告)号：US09653430B2

公开(公告)日：2017-05-16

申请号：US14955124

申请日：2015-12-01

Applicant: Taeyeong Kim ,  Byung Lyul Park ,  Seokho Kim ,  Pil-Kyu Kang ,  Hyoju Kim ,  Jin Ho An ,  Joo Hee Jang

Inventor： Taeyeong Kim ,  Byung Lyul Park ,  Seokho Kim ,  Pil-Kyu Kang ,  Hyoju Kim ,  Jin Ho An ,  Joo Hee Jang

IPC: H01L25/065 ,  H01L21/66 ,  H01L23/00 ,  H01L23/48 ,  H01L23/528 ,  H01L23/31 ,  H01L21/683 ,  H01L21/768

CPC classification number: H01L25/0657 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L22/32 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2224/03002 ,  H01L2224/03616 ,  H01L2224/0392 ,  H01L2224/04 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/08146 ,  H01L2224/09181 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/14515 ,  H01L2224/16146 ,  H01L2224/73251 ,  H01L2224/80201 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80907 ,  H01L2224/92 ,  H01L2224/9222 ,  H01L2224/94 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06596 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2224/80 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/81 ,  H01L2224/08 ,  H01L2224/16 ,  H01L2924/00012 ,  H01L22/00 ,  H01L21/304 ,  H01L2221/68304 ,  H01L2221/68381 ,  H01L21/78

Abstract: Semiconductor devices having stacked structures and methods for fabricating the same are provided. A semiconductor device includes at least one single block including a first semiconductor chip and a second semiconductor chip stacked thereon. Each of the first and second semiconductor chips includes a semiconductor substrate including a through-electrode, a circuit layer on a front surface of the semiconductor substrate, and a front pad that is provided in the circuit layer and is electrically connected to the through-electrode. The surfaces of the semiconductor substrates face each other. The circuit layers directly contact each other such that the semiconductor chips are bonded to each other.

公开(公告)号：US20160358881A1

公开(公告)日：2016-12-08

申请号：US14917318

申请日：2014-12-18

Applicant: EV GROUP E. THALLNER GMBH

Inventor： Andreas FEHKUHRER

IPC: H01L23/00 ,  B32B37/00 ,  H01L21/683 ,  B32B38/18 ,  H01L23/544 ,  H01L25/00

CPC classification number: H01L24/80 ,  B32B37/0046 ,  B32B38/1841 ,  B32B38/1858 ,  B32B2309/105 ,  B32B2457/14 ,  H01L21/187 ,  H01L21/304 ,  H01L21/67092 ,  H01L21/6831 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/544 ,  H01L24/08 ,  H01L24/74 ,  H01L24/75 ,  H01L24/94 ,  H01L24/95 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68363 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/0224 ,  H01L2224/0381 ,  H01L2224/0382 ,  H01L2224/03831 ,  H01L2224/0384 ,  H01L2224/08121 ,  H01L2224/08145 ,  H01L2224/74 ,  H01L2224/75251 ,  H01L2224/75272 ,  H01L2224/75701 ,  H01L2224/75702 ,  H01L2224/75704 ,  H01L2224/75705 ,  H01L2224/75724 ,  H01L2224/75725 ,  H01L2224/75734 ,  H01L2224/75735 ,  H01L2224/75744 ,  H01L2224/75745 ,  H01L2224/7598 ,  H01L2224/80 ,  H01L2224/80003 ,  H01L2224/80006 ,  H01L2224/8001 ,  H01L2224/80011 ,  H01L2224/8002 ,  H01L2224/80047 ,  H01L2224/80051 ,  H01L2224/80093 ,  H01L2224/80099 ,  H01L2224/8013 ,  H01L2224/80132 ,  H01L2224/80201 ,  H01L2224/80203 ,  H01L2224/80209 ,  H01L2224/80213 ,  H01L2224/80801 ,  H01L2224/80894 ,  H01L2224/80907 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2224/97 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2221/68304

Abstract: A method for bonding a first substrate with a second substrate, characterized in that the first substrate and/or the second substrate is/are thinned before the bonding.

Abstract translation: 一种用于将第一衬底与第二衬底结合的方法，其特征在于，在所述接合之前所述第一衬底和/或所述第二衬底被薄化。