公开(公告)号：EP0520662A3

公开(公告)日：1993-09-22

申请号：EP92305475.3

申请日：1992-06-15

Applicant: TDK Corporation

Inventor： Nakagawa, Shiro ,  Tsuchida, Atsuko ,  Takahashi, Eiji

IPC: H03M1/20

CPC classification number: H03M1/201

Abstract: An A/D converter system has an A/D converter element (10) which provides a first predetermined number of digital output bits for each input analog signal, an addition means (12,70) for adding linear slope potential to said input analog signal, and a calculator (14) for providing an average of a plurality of digital output signals of said A/D converter element so that said average has larger number of bits than said first predetermined number. Said addition means is implemented by a time constant circuit (70) which functions as an integral circuit for an input analog signal, and functions as a differential circuit for a slope potential.

公开(公告)号：EP0444234A1

公开(公告)日：1991-09-04

申请号：EP90104107.9

申请日：1990-03-02

Applicant: Siemens Elema AB ,  SIEMENS AKTIENGESELLSCHAFT

Inventor： Hjorth, Bo, Ing. ,  Ohlsson, Thomas, Dipl.-Ing.

IPC: H03M1/18

CPC classification number: H03M1/183 ,  H03M1/201

Abstract: Die Erfindung betrifft ein Verfahren und eine Einrichtung zur Analog/Digital-Wandlung eines sich zeitlich ändernden elektrischen Eingangssignals (ES). Dabei wird das Ergebnis der Analog/Digital-Wandlung mittels einer elektronischen Recheneinrichtung (6) unter Heranziehung von sowohl dem dynamischen Anteil (AS) des Eingangssignals (ES) als auch dem Gleichspannungsanteil des Eingangssignals (ES) entsprechenden und getrennt voneinander gebildeten Ausgangsdaten eines Analog/Digital-Wandlers (4) in einer solchen Weise ermittelt, daß die resultierende bit-Anzahl der Ergebnisse der Analog/Digital-Wandlung größer als die bit-Anzahl des Analog/Digital-Wandlers (4) ist.

Abstract translation: 本发明涉及一种随时间变化的电输入信号（ES）的模拟/数字转换的方法和装置。 模拟/数字转换的结果通过使用与输入信号（ES）的动态分量（AS）和输入信号的直流电压分量相对应的输出数据的电子计算机（6）来确定 （ES）并且以模拟/数字转换器的结果的比特数大于模拟/数字转换器（4）的比特数的方式彼此分离地形成模数/数字转换器（4） 转换器（4）。 ... ...

公开(公告)号：EP0179056B1

公开(公告)日：1990-08-22

申请号：EP84901896.5

申请日：1984-04-20

Applicant: MOTOROLA, INC.

Inventor： JANC, Robert, Vincent

IPC: H03M1/20 ,  H04B1/06

CPC classification number: H03M1/201 ,  H04B14/046

Abstract: A sample and hold circuit (10) receives a low level analog input signal and is gated by a clock (18). The output of the sample and hold circuit (10) is summed with a signal from a noise source (22) and the resulting signal coupled to an analog to digital (A/D) converter (24). The noise source (22) presents a bandwidth restricted signal having no substantial energy in the range of frequencies of the desired analog input signal. The clock (18) also drives the A/D convertor (24) which has a plurality of digital output signals (26) which correspond to varying analog signal levels. The resulting signal contains a signal component corresponding to the input signal which is converted into a digital representation by the A/D convertor (24) even though the magnitude of the input signal is less than the threshold sensitivity of the A/D convertor (24).

公开(公告)号：EP3482164B1

公开(公告)日：2024-09-04

申请号：EP16741531.4

申请日：2016-07-08

IPC: G01F1/66

CPC classification number: G01F1/667 ,  H03M1/12 ,  H03M1/201

公开(公告)号：EP2913890B1

公开(公告)日：2017-12-06

申请号：EP15155180.1

申请日：2015-02-16

Applicant: Elta Systems Ltd.

Inventor： Fleishman, Baruch

IPC: H01Q3/26 ,  H03M1/06 ,  H03M1/20 ,  H04B7/08 ,  H03M3/00 ,  H04B1/00

CPC classification number: H03M1/201 ,  H04B1/0007 ,  H04B7/086

Abstract: A system and method for enhancing a dynamic range of a beamforming multichannel digital receiver are described. The receiver comprises a plurality of receiving channels, each including an analog-to-digital converter configured for converting an analog input signal generated by antenna elements into a digital signal. A "spatial" dither signal is used to decorrelate the quantization noise of the analog-to-digital converters. A dither signal is generated and split into a predetermined number of coherent dithering signals. The method includes providing predetermined time delays to the coherent dithering signals, and adding the delayed coherent dithering signals to the input signals in each receiving channel, correspondingly, thereby creating a dither signal equivalent to a signal arriving from a certain specific direction out-of-field-of-view of the antenna array. Removing of the dither signal based on the direction of arrival, is implemented during beamforming signal processing, thus enhancing the dynamic range of electromagnetic signals arriving within a field-of-view of the antenna array.

公开(公告)号：EP3198726A1

公开(公告)日：2017-08-02

申请号：EP15767518.2

申请日：2015-09-25

Applicant: Continental Teves AG & Co. OHG

Inventor： ACKER, Heinrich

IPC: H03M1/20

CPC classification number: H03M1/0626 ,  H03M1/002 ,  H03M1/0614 ,  H03M1/1009 ,  H03M1/124 ,  H03M1/201 ,  H03M1/60

Abstract: The invention relates to a device for digitizing an analogue signal, wherein a distortion signal outlet of a distortion signal generator is only coupled to an analogue digital converter by means of passive components.

Abstract translation: 本发明涉及一种用于数字化模拟信号的装置，其中失真信号发生器的失真信号输出端仅通过无源部件耦合到模数转换器。

公开(公告)号：EP2546992B1

公开(公告)日：2014-03-05

申请号：EP11173743.3

申请日：2011-07-13

Applicant: IMEC

Inventor： Verbruggen, Bob ,  Craninckx, Jan

IPC: H03M1/04 ,  H03M1/20 ,  H03M1/16 ,  H03M1/44 ,  H03M1/46

CPC classification number: H03M1/201 ,  H03M1/04 ,  H03M1/164 ,  H03M1/44 ,  H03M1/46

公开(公告)号：EP2546992A1

公开(公告)日：2013-01-16

申请号：EP11173743.3

申请日：2011-07-13

Applicant: IMEC

Inventor： Verbruggen, Bob ,  Craninckx, Jan

IPC: H03M1/04 ,  H03M1/20 ,  H03M1/16 ,  H03M1/44 ,  H03M1/46

CPC classification number: H03M1/201 ,  H03M1/04 ,  H03M1/164 ,  H03M1/44 ,  H03M1/46

Abstract: The present invention is related to an analog-to-digital (A/D) converter circuit arranged for receiving an analog input signal (1) and for outputting a digital representation (6) of said analog input signal (1). The A/D converter circuit comprises:
- a first converter stage (2) configured for receiving the analog input signal (1) and for generating a first set (3) of conversion bits, a first completion signal (7) and a residual analog output signal (4) representing the difference between the analog input signal and a signal represented by said first set of conversion bits,
- a second converter stage (5) comprising
o a clock generation circuit (8) arranged for receiving the first completion signal and for generating a clock signal,
o a plurality of comparators each being configured for receiving the residual analog output signal and a common reference voltage, said plurality of comparators arranged for being activated by the clock signal and for outputting a plurality of comparator decisions,
o a digital processing stage (9) configured for receiving the plurality of comparator decisions and for generating a second set of conversion bits,

- means for generating the digital representation of the analog input signal by combining the first and second set of conversion bits.

Abstract translation: 本发明涉及一种被配置用于接收模拟输入信号（1）并用于输出所述模拟输入信号（1）的数字表示（6）的模拟（A / D）转换器电路。 A / D转换器电路包括： - 第一转换器级（2），被配置为接收模拟输入信号（1）并产生第一组（3）转换位，第一完成信号（7）和残余模拟 输出信号（4），其表示模拟输入信号和由所述第一组转换位表示的信号之间的差; - 第二转换器级（5），包括被设置用于接收第一完成信号的时钟产生电路（8） 生成时钟信号，多个比较器被配置为用于接收残余模拟输出信号和公共参考电压，所述多个比较器被布置成被时钟信号激活并用于输出多个比较器判定，数字处理阶段 （9），被配置为用于接收所述多个比较器判定并用于生成第二组转换位; - 用于生成所述转换位的数字表示的装置 模拟输入信号通过组合第一和第二组转换位。

公开(公告)号：EP0538252B1

公开(公告)日：1996-12-04

申请号：EP90911030.6

申请日：1990-07-12

Applicant: BIO-RAD LABORATORIES, INC.

Inventor： CURBELO, Raul

IPC: G01J3/00 ,  G01J3/453 ,  G01R23/16 ,  H03M1/08 ,  H03M1/20

CPC classification number: G01J3/453 ,  H03M1/201

Abstract: A technique for improving the resolution of an A/D converter (30). The input analog signal is sampled to generate an analog level and the analog level is held (20) for an interval. A dither signal (22) is superimposed (23) on the held level to generate a fluctuating voltage. This fluctuating voltage is then sampled (25) a plurality of at least N times, and N sampled values are communicated to the A/D converter (30) so that N digitized values are generated. These digitized values are averaged (32) to provide an output having a digitization error reduced by a factor of up to N1/2.

公开(公告)号：EP0538252A4

公开(公告)日：1993-11-03

申请号：EP90911030

申请日：1990-07-12

Applicant: BIO-RAD LABORATORIES, INC.

Inventor： CURBELO, RAUL

IPC: G01J3/45 ,  G01J3/00 ,  G01J3/453 ,  G01R23/16 ,  H03M1/08 ,  H03M1/20

CPC classification number: G01J3/453 ,  H03M1/201

Abstract: A technique for improving the resolution of an A/D converter (30). The input analog signal is sampled to generate an analog level and the analog level is held (20) for an interval. A dither signal (22) is superimposed (23) on the held level to generate a fluctuating voltage. This fluctuating voltage is then sampled (25) a plurality of at least N times, and N sampled values are communicated to the A/D converter (30) so that N digitized values are generated. These digitized values are averaged (32) to provide an output having a digitization error reduced by a factor of up to N .