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公开(公告)号：US08941224B2
公开(公告)日：2015-01-27
申请号：US13853281
申请日：2013-03-29
Applicant: Kinsus Interconnect Technology Corp.
Inventor： Ting-Hao Lin , Yu-Te Lu , De-Hao Lu
IPC: H01L23/06 , H01L23/498
CPC classification number: H01L23/49827 , H01L21/563 , H01L23/49861 , H01L23/49894 , H01L23/562 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/0002 , H01L2924/00
Abstract: A package structure includes a thin chip substrate, a stabilizing material layer, a chip and a filling material. A first circuit metal layer of the substrate is inlaid into a dielectric layer and a co-plane is defined by the first circuit metal layer and the dielectric layer and is exposed from the dielectric layer. The bonding pads of the substrate are on the co-plane, have a height higher than the co-plane and connected to the first circuit metal layer. The stabilizing material layer is provided on two sides of the co-plane to define a receiving space for accommodating the chip. The filling material is injected into the receiving space to fasten the pins of the chip securely with bonding pads. Since no plastic molding is required, a total thickness of the package structure and the cost is reduced. The stabilizing material layer prevents the substrate from warping and distortion.
Abstract translation: 封装结构包括薄片基板，稳定材料层，芯片和填充材料。 衬底的第一电路金属层嵌入电介质层中，并且由第一电路金属层和电介质层限定共面，并从电介质层露出。 衬底的接合焊盘在共面上，具有高于共面的高度并连接到第一电路金属层。 稳定材料层设置在共面的两侧，以限定用于容纳芯片的容纳空间。 将填充材料注入到接收空间中，用粘合垫牢固地固定芯片的销。 由于不需要塑料成型，所以包装结构的总厚度和成本降低。 稳定材料层防止基材翘曲和变形。
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公开(公告)号：US20140291853A1
公开(公告)日：2014-10-02
申请号：US13853281
申请日：2013-03-29
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Ting-Hao Lin , Yu-Te Lu , De-Hao Lu
IPC: H01L23/498
CPC classification number: H01L23/49827 , H01L21/563 , H01L23/49861 , H01L23/49894 , H01L23/562 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/0002 , H01L2924/00
Abstract: A package structure includes a thin chip substrate, a stabilizing material layer, a chip and a filling material. A first circuit metal layer of the substrate is inlaid into a dielectric layer and a co-plane is defined by the first circuit metal layer and the dielectric layer and is exposed from the dielectric layer. The bonding pads of the substrate are on the co-plane, have a height higher than the co-plane and connected to the first circuit metal layer. The stabilizing material layer is provided on two sides of the co-plane to define a receiving space for accommodating the chip. The filling material is injected into the receiving space to fasten the pins of the chip securely with bonding pads. Since no plastic molding is required, a total thickness of the package structure and the cost is reduced. The stabilizing material layer prevents the substrate from warping and distortion.
Abstract translation: 封装结构包括薄片基板，稳定材料层，芯片和填充材料。 衬底的第一电路金属层嵌入电介质层中，并且由第一电路金属层和电介质层限定共面，并从电介质层露出。 衬底的接合焊盘在共面上，具有高于共面的高度并连接到第一电路金属层。 稳定材料层设置在共面的两侧，以限定用于容纳芯片的容纳空间。 将填充材料注入到接收空间中，用粘合垫牢固地固定芯片的销。 由于不需要塑料成型，所以包装结构的总厚度和成本降低。 稳定材料层防止基材翘曲和变形。
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公开(公告)号：US08547548B1
公开(公告)日：2013-10-01
申请号：US13721019
申请日：2012-12-20
Applicant: Kinsus Interconnect Technology Corp.
Inventor： Chia-Chi Lo , Cheng-Hsiung Yang Yang , Jun-Chung Hsu
IPC: G01N21/00
CPC classification number: G01N21/8803 , G01N2021/8861 , G01N2021/888
Abstract: Disclosed is a final defect inspection system, which including a host device, a microscope, a bar code scanner, a support tool, a signal transceiver and an electromagnetic pen. The bar code scanner scans a bar code on a circuit board provided on the support plate. The host device selects data and a circuit layout diagram from the database corresponding to the bar code. The signal transceiver and the electromagnetic pen are electrically connected to the host device. The electromagnetic pen is used to make a mark on a scrap region of the circuit board where any defect is visually found through the microscope. The signal transceiver receives and transmits the positions of the mark to the host device such that the host device calculates the coordinate of a scrap region based on a relative position between an original point and the positions of the mark.
Abstract translation: 公开了一种最终缺陷检查系统，其包括主机，显微镜，条形码扫描器，支持工具，信号收发器和电磁笔。 条形码扫描器扫描设置在支撑板上的电路板上的条形码。 主机设备从与条形码对应的数据库中选择数据和电路布局图。 信号收发器和电磁笔电连接到主机设备。 电磁笔用于在电路板的废料区域上形成标记，其中通过显微镜在视觉上发现任何缺陷。 信号收发器接收和发送标记的位置到主机设备，使得主机设备基于原始点和标记位置之间的相对位置来计算废料区域的坐标。
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84.发明授权公开(公告)号：US11044806B2
公开(公告)日：2021-06-22
申请号：US16718100
申请日：2019-12-17
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Chin-Kuan Liu , Chao-Lung Wang , Shuo-Hsun Chang , Yu-Te Lu , Chin-Hsi Chang
Abstract: A multi-layer circuit structure is disposed on the delivery loading plate through the bottom-layer circuit structure, the delivery loading plate exposes the conductive corrosion-barrier layer, and the top-layer circuit of the multi-layer circuit structure is electrically connected to the conductive corrosion-barrier layer through the bottom-layer circuit and the electrical connection layer. Therefore, before the multi-layer circuit board is delivered to the assembly company or before the multi-layer circuit board is packaged with chips, an electrical testing can be applied to the multi-layer circuit board.
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公开(公告)号：US20190387631A1
公开(公告)日：2019-12-19
申请号：US16555261
申请日：2019-08-29
Applicant: Kinsus Interconnect Technology Corp.
Inventor： Ting-Hao Lin , Chiao-Cheng Chang , Yi-Nong Lin
Abstract: A manufacturing method of a double layer circuit board comprises forming a connecting pillar on a first circuit, wherein the connecting pillar comprises a first end, connected to the first circuit, and a second end, opposite to the first end; forming a substrate on the first circuit and the connecting pillar; drilling the substrate to expose a portion of the second end of the connecting pillar, wherein the other portion of the second end of the connecting pillar is covered by the substrate; and forming a second circuit on the substrate and the portion of the second end of the connecting pillar, wherein an area of the first end connected to the first circuit layer is greater than an area of the portion of the second end connected to the second circuit layer.
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Patent Agency Ranking
公开(公告)号：US10440836B2
公开(公告)日：2019-10-08
申请号：US15138261
申请日：2016-04-26
Applicant: Kinsus Interconnect Technology Corp.
Inventor： Ting-Hao Lin , Chiao-Cheng Chang , Yi-Nong Lin
Abstract: Provided is a double layer circuit board and a manufacturing method thereof. The double layer circuit board comprises a substrate, a first circuit layer formed on a first surface of the substrate, a second circuit layer formed on a second surface of the substrate, and at least one connecting pillar formed in and covered by the substrate. Each one of the at least one connecting pillar includes a first end connected to the first circuit layer and a second end connected to the second circuit layer. A terminal area of the second end is greater than a terminal area of the first end. Therefore, the second circuit layer is firmly connected to the first circuit layer through the at least one connecting pillar. A yield rate of the double layer circuit board may be increased.
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公开(公告)号：US10334719B2
公开(公告)日：2019-06-25
申请号：US15826692
申请日：2017-11-30
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Chin-Kuan Liu , Chao-Lung Wang , Shuo-Hsun Chang , Yu-Te Lu , Chin-Hsi Chang
Abstract: A multi-layer circuit board capable of being applied with electrical testing includes a patterned metal-interface layer, a metallic delivery loading plate, an electrical connection layer, a conductive corrosion-barrier layer, a bottom dielectric layer, and a multi-layer circuit structure. The multi-layer circuit structure is disposed on the delivery loading plate through the bottom dielectric layer. The top-layer circuit of the multi-layer circuit structure is electrically connected to the conductive corrosion-barrier layer through the bottom-layer circuit and the electrical connection layer. The delivery loading plate and the patterned metal-interface layer expose the conductive corrosion-barrier layer. Therefore, before the multi-layer circuit board is packaged, an electrical testing can be applied to the multi-layer circuit board to check if it can be operated normally. Hence, costs for figuring out reasons of the unqualified electronic component can be reduced, and responsibilities for the unqualified electrical testing result of the electronic component can be clarified.
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公开(公告)号：US20190189335A1
公开(公告)日：2019-06-20
申请号：US16285138
申请日：2019-02-25
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Ting-Hao Lin , Chiao-Cheng Chang , Yi-Nong Lin
CPC classification number: H01F27/2804 , H01F2027/2809 , H05K1/0393 , H05K1/113 , H05K1/118 , H05K1/165 , H05K3/4617 , H05K3/4644
Abstract: A buildup board structure incorporating magnetic induction coils and flexible boards is disclosed. The buildup board structure includes at least one first buildup unit or at least one second buildup unit. The first buildup unit includes at least one first buildup body, the second buildup unit includes at least one second buildup body. Any two adjacent buildup bodies are separated by a covering layer provided with a central hole for electrical insulation. All central holes are aligned. Each buildup body includes a plurality of flexible boards, and each flexible board is embedded with a plurality of magnetic induction coils surrounding the corresponding central hole and connected through connection pads. The first and/or second buildup bodies are easily laminated in any order by any number as desired such that the effect of magnetic induction provided by the magnetic induction coils embedded in the buildup board structure are addable to greatly enhance the overall effect of magnetic induction.
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公开(公告)号：US10256028B2
公开(公告)日：2019-04-09
申请号：US15086333
申请日：2016-03-31
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Ting-Hao Lin , Chiao-Cheng Chang , Yi-Nong Lin
Abstract: A buildup board structure incorporating magnetic induction coils and flexible boards is disclosed. The buildup board structure includes at least one first, second and third buildup bodies modular and stackable. Any two adjacent buildup bodies are separated by a covering layer provided with a central hole for electrical insulation. All central holes are aligned. Each buildup body includes a plurality of flexible boards, and each flexible board is embedded with a plurality of magnetic induction coils surrounding the corresponding central hole and connected through connection pads. The first, second and third buildup bodies are easily laminated in any order by any number as desired such that the effect of magnetic induction provided by the magnetic induction coils embedded in the buildup board structure are addable to greatly enhance the overall effect of magnetic induction.
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90.发明申请公开(公告)号：US20190059154A1
公开(公告)日：2019-02-21
申请号：US15826694
申请日：2017-11-30
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Chin-Kuan Liu , Chao-Lung Wang , Shuo-Hsun Chang , Yu-Te Lu , Chin-Hsi Chang
Abstract: A multi-layer circuit board capable of being applied with electrical testing includes a metallic delivery loading plate, a bottom-layer circuit structure, a conductive corrosion-barrier layer, and a multi-layer circuit structure. The bottom-layer circuit structure is overlapping on the delivery loading plate. The conductive corrosion-barrier layer is disposed on the bottom dielectric layer. The multi-layer circuit structure is overlapping on the bottom-layer circuit structure. The top-layer circuit of the multi-layer circuit structure is electrically connected to the conductive corrosion-barrier layer through the inner-layer circuit of the multi-layer circuit structure and the bottom-layer circuit of the bottom-layer circuit structure. The delivery loading plate and the bottom dielectric layer of the bottom-layer circuit structure expose the conductive corrosion-barrier layer. Therefore, before the multi-layer circuit board is packaged, an electrical testing can be applied to the multi-layer circuit board to check if it can be operated normally.
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