公开(公告)号：EP0760555A1

公开(公告)日：1997-03-05

申请号：EP95830369.5

申请日：1995-08-31

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Brambilla, Davide ,  Nebuloni, Daniela ,  Rossi, Giorgio ,  Lecce, Sergio

IPC: H03F3/345 ,  G05F3/26

CPC classification number: H03F3/345 ,  G05F3/267

Abstract: A current generator circuit with controllable frequency response is of a type which comprises at least one current mirror formed of MOS transistors, being powered through a terminal held at a constant voltage, having an input leg through which a reference current (I1) is driven by a first current generator (G1), and having an output leg for generating, on an output terminal (OUT) of the mirror, a mirrored current (I out ) which is proportional to the reference current (I1). The input leg includes at least a first transistor (M1) which is diode-connected and has a control terminal (Ga1) coupled to a corresponding terminal (Ga2) of a second transistor (M2) included in the output leg.
In accordance with the invention, the mirror circuit further comprises an impedance matching means (3) connected across the control terminals (Ga1 and Ga2) of the first and second transistors and configured to hold the same voltage value at both terminals (Ga1 and Ga2). The impedance matching means (3) has an adjustable output impedance, specifically lower in value than the value to be had without this means. It functions to regulate the impedance on the control node (Ga2) of the second transistor (M2).
The invention is equally applicable to N-channel and P-channel MOS transistors.
Advantageously, the reference current can be varied by an external signal which is a function of the output signal, to provide feedback regulating features.

Abstract translation: 具有可控频率响应的电流发生器电路是一种类型，其包括由MOS晶体管形成的至少一个电流镜，通过保持在恒定电压的端子供电，具有输入支路，参考电流（I1）通过该输入支路由 第一电流发生器（G1），并且具有用于在所述反射镜的输出端子（OUT）上产生与所述参考电流（I1）成比例的镜像电流（Iout）的输出支路。 输入支路至少包括二极管连接的第一晶体管（M1），并且具有耦合到包括在输出支路中的第二晶体管（M2）的相应端子（Ga2）的控制端子（Ga1）。 根据本发明，镜电路还包括连接在第一和第二晶体管的控制端（Ga1和Ga2）两端的阻抗匹配装置（3），并被配置为在两端（Ga1和Ga2）处保持相同的电压值， 。 阻抗匹配装置（3）具有可调节的输出阻抗，具体值低于没有这种方法的值。 它用于调节第二晶体管（M2）的控制节点（Ga2）上的阻抗。 本发明同样适用于N沟道和P沟道MOS晶体管。 有利地，参考电流可以通过作为输出信号的函数的外部信号来改变，以提供反馈调节特征。

公开(公告)号：EP0545074B1

公开(公告)日：1997-03-05

申请号：EP92118573.2

申请日：1992-10-30

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Ghezzi, Paolo ,  Pio, Federico ,  Riva, Carlo

IPC: H01L21/82

CPC classification number: H01L27/11521 ,  H01L27/11558

公开(公告)号：EP0757358A1

公开(公告)日：1997-02-05

申请号：EP95830357.0

申请日：1995-08-04

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Pascucci, Luigi

IPC: G11C16/06

CPC classification number: G11C16/26

Abstract: The reading circuit described comprises, for each bit line (BL) of a matrix (11) of memory cells (12), a controllable switching element (To) which can connect the bit line (BL) to a voltage source (V DD ) in response to a control signal applied to a control terminal thereof, a detector stage (16) sensitive to the flow of current through the bit line (BL), and a driving stage (15) comprising two field-effect transistors (TNB, TPB) connected in the inverter configuration with the input of the inverter connected to the bit line (BL) and with the output (CAS) of the inverter connected to the control terminal of the controllable switching element (To). In order to charge the capacitance (C BL ) associated with the bit line rapidly but without causing oscillatory phenomena, the driving stage (15) comprises means (Tnat, Tas) for reducing the gain of the feedback loop formed by the inverter (TNB, TPB) and by the controllable switching element (To).

Abstract translation: 所描述的读取电路对于存储器单元（12）的矩阵（11）的每个位线（BL）包括可控开关元件（To），其可将位线（BL）连接到电压源（VDD） 响应于施加到其控制端的控制信号，对通过位线（BL）的电流流敏感的检测器级（16）以及包括两个场效应晶体管（TNB，TPB）的驱动级（15） 连接在变频器配置中，变频器的输入连接到位线（BL），变频器的输出（CAS）连接到可控开关元件（To）的控制端子。 为了快速地对与位线相关联的电容（CBL）进行充电，但不产生振荡现象，驱动级（15）包括用于降低由逆变器（TNB，TPB）形成的反馈回路的增益的装置（Tnat，Tas） ）和可控开关元件（To）。

公开(公告)号：EP0757341A1

公开(公告)日：1997-02-05

申请号：EP95830350.5

申请日：1995-08-01

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Baldi, Livio

IPC: G09G1/00 ,  H01J31/12 ,  H01J9/02

CPC classification number: G09G3/22 ,  H01J1/3042 ,  H01J31/127 ,  H01J2201/30403 ,  H01J2201/319 ,  H01J2329/00

Abstract: A pixel emission current limiting resistance is realized by forming a stack of alternately doped amorphous or polycrystalline silicon layers over the cathodic conductors of a FED driving matrix. The stack of amorphous or polycrystalline silicon layers doped alternately n and p provides at least a reversely biased n/p junction having a leakage current that matches the required level of pixel emission current. The reversely biased junction constitutes a nonlinear series resistance that is quite effective in limiting the emission current through anyone of the microtips that form an individually excitable pixel and which are formed on the uppermost layer of the stack.

Abstract translation: 像素发射电流限制电阻是通过形成可替换的堆叠掺杂在FED驱动矩阵的阴极导体非晶硅或多晶硅层实现。 非晶硅或多晶硅层的堆叠掺杂替代地n和p提供至少一个反向偏置N / P结具有漏电流没有发射电流像素的所需的电平相匹配。 的反向偏置结构成非线性串联电阻所做的是在通过微尖的任何限制发射电流非常有效，在独立可激发的像素确实形式和其上形成有堆叠的最上层上。

公开(公告)号：EP0504979B1

公开(公告)日：1997-01-22

申请号：EP92200689.5

申请日：1992-03-11

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Brambilla, Massimiliano ,  Poletto, Vanni

IPC: G01R1/28 ,  G05F1/46 ,  G05F1/567

CPC classification number: G01R1/28 ,  Y10S323/907

公开(公告)号：EP0459578B1

公开(公告)日：1997-01-22

申请号：EP91201245.7

申请日：1991-05-25

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l. ,  CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Zambrano, Raffaele ,  Grimaldi, Antonio

IPC: H01L27/06 ,  H01L29/772 ,  H01L29/06

CPC classification number: H01L27/0623

公开(公告)号：EP0753934A1

公开(公告)日：1997-01-15

申请号：EP95830301.8

申请日：1995-07-13

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Masini, Marco ,  Tavazzani, Claudio ,  Boiocchi, Stefania

IPC: H03F3/00 ,  H03F3/217 ,  H03K3/282

CPC classification number: H03K3/2821 ,  H03F3/2171

Abstract: An amplifier (70) is formed by an astable multivibrator (2) having a signal output (15, 19) supplying a two-state output signal to a power stage (3), the output (35) of which presents an output voltage (V o ) switching between a first and second value; the output voltage presents a duty cycle varying with the input signal (V in ) of the multivibrator. The amplifier (70) is connected between a first and second supply line (V cc , -V cc ) symmetrical with respect to ground (13) and subject to supply noise ( ΔV), and comprises a current source (71) for generating the bias current of the astable multivibrator and supplying a current (I) switchable at each half cycle; the value of the current at each half cycle being proportional to the absolute value of the output voltage (V o ) of the amplifier, so as to vary the duty cycle of the amplifier in a manner correlated with the supply noise, so that the average output voltage value is zero.

Abstract translation: 放大器（70）由具有向功率级（3）提供两状态输出信号的信号输出（15,19）的非稳态多谐振荡器（2）形成，其输出（35）呈现输出电压（ Vo）在第一和第二值之间切换; 输出电压呈现与多谐振荡器的输入信号（Vin）变化的占空比。 放大器（70）连接在相对于地（13）对称并经受电源噪声（DELTA V）的第一和第二电源线（Vcc，-Vcc）之间，并且包括用于产生偏置的电流源（71） 提供不稳定多谐振荡器的电流并提供每个半周期可切换的电流（I）; 每个半周期的电流值与放大器的输出电压（Vo）的绝对值成正比，从而以与供给噪声相关的方式改变放大器的占空比，使平均输出 电压值为零。

公开(公告)号：EP0753859A1

公开(公告)日：1997-01-15

申请号：EP95830302.6

申请日：1995-07-14

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Sali, Mauro ,  Dallabora, Marco ,  Carrera, Marcello

IPC: G11C16/06 ,  G11C29/00

CPC classification number: G11C16/3459 ,  G06F2201/81 ,  G11C16/04 ,  G11C16/3454 ,  G11C29/028 ,  G11C29/50 ,  G11C2029/5006

Abstract: A method for setting the threshold voltage of a reference memory cell (RMC) of a memory device is described, the reference memory cell (RMC) being used as a reference current generator for generating a reference current which is compared by a sensing circuit (1,2,3) of the memory device with currents sunk by memory cells to be sensed, belonging to a memory matrix (MM) of the memory device. The method comprises a first step in which the reference memory cell (RMC) is submitted to a change in its threshold voltage, and a second step in which the threshold voltage of the reference memory cell (RMC) is verified. The second step provides for performing a sensing of the reference memory cell (RMC) using a memory cell (MC) with known threshold voltage (V TUV ) belonging to the memory matrix (MM) as a reference current generator for generating a current (IC) which is compared by the sensing circuit (1,2,3) with the current (IR) sunk by the reference memory cell (RMC).

Abstract translation: 描述了用于设置存储器件的参考存储单元（RMC）的阈值电压的方法，参考存储单元（RMC）用作参考电流发生器，用于产生参考电流，该参考电流由感测电路（1 ，2,3）的存储器件，存储器件的存储器矩阵（MM）属于存储器器件的存储器矩阵（MM）。 该方法包括第一步骤，其中参考存储器单元（RMC）被提交到其阈值电压的改变，以及第二步骤，其中验证参考存储单元（RMC）的阈值电压。 第二步提供使用具有属于存储矩阵（MM）的已知阈值电压（VTUV）的存储单元（MC）作为参考电流发生器来执行对参考存储单元（RMC）的感测作为参考电流发生器，用于产生电流（IC） 其通过感测电路（1,2,3）与由参考存储器单元（RMC）沉没的当前（IR）进行比较。

公开(公告)号：EP0536094B1

公开(公告)日：1996-12-11

申请号：EP92830522.6

申请日：1992-09-24

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Daniele, Vincenzo ,  Benedetti, Mirella

IPC: H03K17/693

CPC classification number: H03K17/693 ,  H03K17/6235 ,  H03K17/6872 ,  H03K2217/0036

公开(公告)号：EP0744829A1

公开(公告)日：1996-11-27

申请号：EP95830217.6

申请日：1995-05-22

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Tomasini, Luciano ,  Castello, Rinaldo ,  Bietti, Ivan ,  Clerici, Giancarlo

IPC: H03H1/00 ,  H03F3/45

CPC classification number: H03F3/45475 ,  H03F3/45982 ,  H03F2203/45526

Abstract: The high-pass filter described comprises at least one circuit unit constituted by a first branch (A) and a second branch (B) both connected to an input (IN) of the filter on one side and, on the other side, to an adder (OP) the output of which is the output (OUT) of the filter. The first branch (A) comprises means (Rff) for transferring an input signal substantially without modifying its frequency content, and the second branch (B) comprises a low-pass filter (Rsc, C'fil). The whole is of dimensions such that the components of the input signal with frequencies below the cut-off frequency of the low-pass filter are substantially cancelled out at the output of the adder.
The filter is suitable for being produced within a particularly small area in an integrated circuit.

Abstract translation: 所描述的高通滤波器包括由第一分支（A）和第二分支（B）构成的至少一个电路单元，其两端都连接到一侧的滤波器的输入端（IN），另一侧连接到 加法器（OP），其输出是滤波器的输出（OUT）。 第一分支（A）包括用于基本上不修改其频率内容来传送输入信号的装置（Rff），并且第二分支（B）包括低通滤波器（Rsc，C'fil）。 整体尺寸使得低频滤波器的截止频率以下的输入信号的分量在加法器的输出端基本抵消。 该滤波器适用于在集成电路的特别小的区域内产生。