公开(公告)号：EP0598168A1

公开(公告)日：1994-05-25

申请号：EP92830625.7

申请日：1992-11-18

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Baldi, Livio

IPC: H01L23/485 ,  H01L21/285 ,  H01L21/74

CPC classification number: H01L21/28525 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Highly reliable direct contacts (1) may be formed by defining a direct contact area within a larger area (A) purposely implanted and diffused for ensuring electrical continuity in the semiconductor. Patterning may define the contacting polysilicon (1) within an implanted direct contact area (A) so that the definition edges thereof fall on a gate oxide layer (4) thus preventing an etching of the semiconductor (3) during the unavoidable over-etching that concludes the polysilicon patterning step. Preferably, a pre-definition of the direct contact area is performed through a first deposited layer of polysilicon, which effectively protects a gate oxide layer during a HF wash prior to depositing a second, contacting layer of polysilicon of adequate thickness.

Abstract translation: 可以通过定义在有意植入和扩散的较大区域（A）内的直接接触区域来形成高度可靠的直接接触（1），以确保半导体中的电连续性。 图案化可以限定在植入的直接接触区域（A）内的接触多晶硅（1），使得其定义边缘落在栅极氧化物层（4）上，从而防止在不可避免的过蚀刻期间半导体（3）的蚀刻， 总结多晶硅图案化步骤。 优选地，直接接触区域的预定义通过第一沉积多晶硅层进行，其在沉积足够厚度的多晶硅的第二接触层之前在HF洗涤期间有效地保护栅极氧化物层。

公开(公告)号：EP0575688A3

公开(公告)日：1994-03-16

申请号：EP92830552.3

申请日：1992-10-01

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Ghio, Emilio Giambattista ,  Meroni, Giuseppe ,  Re, Danilo ,  Baldi, Livio

IPC: H01L27/112 ,  H01L21/82

CPC classification number: H01L27/11266 ,  H01L27/112

Abstract: ROM memories made in MOS or CMOS technology with LDD cells may be programmed advantageously in a relatively advanced stage of fabrication by decoupling an already formed drain region from the channel region of cells to be permanently made nonconductive (programmed) by implanting a dopant in an amount sufficient to invert the type of conductivity in a portion of the drain region adjacent to the channel region. In CMOS processes, the programming mask may be a purposely modified mask commonly used for implanting source/drain regions of transistors of a certain type of conductivity. By using high-energy implantation and a dedicated mask, the programming may be effected at even later stages of the fabrication process.

Abstract translation: 采用MOS或CMOS技术制造的具有LDD单元的ROM存储器可以有利地在相对高级的制造阶段通过将已形成的漏极区与单元的沟道区解耦以通过注入一定量的掺杂剂而永久地形成非导电（编程） 足以反转与沟道区相邻的漏极区的一部分中的导电类型。 在CMOS工艺中，编程掩模可以是通常用于注入某种导电类型的晶体管的源极/漏极区的有意修改的掩模。 通过使用高能量注入和专用掩模，编程可以在制造过程的甚至更晚的阶段进行。

公开(公告)号：EP0543254A3

公开(公告)日：1993-12-08

申请号：EP92119191.2

申请日：1992-11-10

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Baldi, Livio

IPC: H01L21/285 ,  H01L21/90 ,  H01L23/485

CPC classification number: H01L21/76843 ,  H01L21/32136 ,  H01L21/76865 ,  H01L21/76877

Abstract: A method of forming high-stability metallic contacts in an integrated circuit with one or more metallized layers provides for a preliminary step of providing a plurality of contact holes (7) in a layer (5) of dielectric material and comprises the steps of:
a) forming a first layer (9) of tungsten on the layer (5) of dielectric material by chemical vapour deposition so as to coat the bases and the walls of the contact holes (7) uniformly, b) forming a second layer (11) of aluminium or an alloy thereof by sputtering deposition on top of the first layer (9) of tungsten so as to fill the holes (7), and c) forming a plurality of metallic interconnections (13) of predetermined geometry by the selective removal of predetermined areas of the superposed aluminium and tungsten layers (9, 11).

公开(公告)号：EP0254973B1

公开(公告)日：1992-07-15

申请号：EP87110269.5

申请日：1987-07-16

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Baldi, Livio ,  Cappelletti, Paolo Giuseppe

IPC: H01L21/308 ,  H01L21/76 ,  H01L21/32

CPC classification number: H01L21/308 ,  H01L21/033 ,  H01L21/763 ,  H01L21/82285 ,  H01L21/823892 ,  H01L27/0928 ,  Y10S148/103

公开(公告)号：EP0788144A1

公开(公告)日：1997-08-06

申请号：EP96830039.2

申请日：1996-01-31

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Baldi, Livio

IPC: H01L21/28 ,  H01L21/336

CPC classification number: H01L29/66825 ,  Y10S438/981

Abstract: A process including the steps of forming a gate oxide layer (50) on a semiconductor substrate (10); masking the gate oxide layer with a nitride mask (52); forming openings (57) in the gate oxide layer (50) using the nitride mask; and forming, at the openings, tunnel oxide regions (19) of a thickness smaller than the thickness of the gate oxide layer. The nitride mask (52) presents a thickness smaller than the width (l) of the openings (57) to improve etching of the gate oxide layer (50) and subsequent washing, protects the covered layers (51) when etching the gate oxide and growing the tunnel oxide regions (19), and is removed easily without damaging the exposed layers.

Abstract translation: 一种方法，包括以下步骤：在半导体衬底（10）上形成栅极氧化物层（50）; 用氮化物掩模（52）掩蔽所述栅极氧化物层; 使用所述氮化物掩模在所述栅极氧化物层（50）中形成开口（57）; 以及在所述开口处形成厚度小于所述栅极氧化物层的厚度的隧道氧化物区域（19）。 氮化物掩模（52）的厚度小于开口（57）的宽度（l），以改善栅极氧化物层（50）的蚀刻和随后的洗涤，在蚀刻栅极氧化物时保护被覆盖层（51），并且 生长隧道氧化物区域（19），并且容易地去除，而不损坏暴露的层。

公开(公告)号：EP0226549A1

公开(公告)日：1987-06-24

申请号：EP86830293.6

申请日：1986-10-09

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Maggioni, Franco ,  Baldi, Livio ,  Cappelletti, Paolo Giuseppe

IPC: H01L21/90 ,  H01L23/52

CPC classification number: H01L27/0688 ,  H01L21/76889 ,  H01L23/528 ,  H01L23/53271 ,  H01L2924/0002 ,  Y10S148/019 ,  Y10S148/106 ,  Y10S148/136 ,  H01L2924/00

Abstract: A monolithic integrated circuit of either the MOS or CMOS type comprises an intermediate layer (8) of polycrystalline silicon, a layer (9) of a silicide of a refractory metal overlying said polycrystalline silicon layer (8), and regions (8a) of preset area and preset paths (9a) formed in the polycrystalline silicon layer (8) and the silicide layer (9); the preset area regions (8a) and preset paths (9a) forming respectively high resistivity resistances and low resistivity interconnection lines for an intermediate connection level.

公开(公告)号：EP0811983A1

公开(公告)日：1997-12-10

申请号：EP96830333.9

申请日：1996-06-06

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Baldi, Livio ,  Maurelli, Alfonso ,  Marangon, Santina ,  Moroni, Maurizio

IPC: G11C11/34 ,  H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11546

Abstract: The device includes flash-EEPROM memory cells (80), circuit transistors (81, 82) and high-voltage transistors (83, 84); and a layer of salicide, i.e. self-aligned titanium silicide, is formed on and contacting the source and drain regions of the cells (80) and transistors (81-84) and on and contacting the control gate regions of the cells and the gate regions of the transistors. The salicide, which reduces the series resistance of the transistors and so improves performance of the circuit portion, in no way impairs the electric characteristics, reliability or cycling characteristics of the cells, thus enabling the formation of mixed devices with a high-performance logic portion and a high storage capacity.

Abstract translation: 该装置包括快闪EEPROM的存储单元（80），电路晶体管（81，82）和高电压晶体管（83，84）; 自对准硅化物和的层，即 自对准硅化钛，是形成在与接触的细胞（80）和晶体管（81-84），而位于该源和漏区和接触细胞与所述晶体管的栅极区的控制栅的区域。 自对准硅化物，这降低了晶体管的串联电阻，因此改进了电路部分的性能，不以任何方式损害电池的电特性，可靠性或循环特性，从而使混合装置具有高性能逻辑部分形成 和高的存储容量。

公开(公告)号：EP0779646A1

公开(公告)日：1997-06-18

申请号：EP95830518.7

申请日：1995-12-14

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Vajana, Bruno ,  Baldi, Livio

IPC: H01L21/00 ,  H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11524

Abstract: A method of fabricating an EEPROM memory cell, including the steps of depositing a thick gate oxide layer on a substrate of P-type semiconductor material; forming on the substrate a tunnel mask of photoresist material presenting a window; implanting N-type ions in the substrate through the window of the tunnel mask to form a continuity region; removing the exposed portion of the gate oxide layer; growing a thin tunnel oxide region on the substrate, at the window of the tunnel mask; depositing a first and second polysilicon layer separated by a dielectric layer; patterning floating gate, control gate and gate oxide regions in self-aligned manner; and forming N-type source and drain regions offset laterally in relation to the gate regions. The implanted continuity region is thus self-aligned with the tunnel region, and lateral diffusion of the dope provides for electric continuity with the drain region.

Abstract translation: 一种制造EEPROM存储单元的方法，包括以下步骤：在P型半导体材料的衬底上沉积厚栅氧化层; 在基板上形成具有窗口的光致抗蚀剂材料的隧道掩模; 通过隧道掩模的窗口将N型离子注入衬底中以形成连续区域; 去除所述栅极氧化物层的暴露部分; 在隧道掩模的窗口处在衬底上生长薄的隧道氧化物区域; 沉积由电介质层分离的第一和第二多晶硅层; 以自对准的方式构图浮置栅极，控制栅极和栅极氧化物区域; 以及形成相对于栅极区域侧向偏移的N型源区和漏区。 植入的连续性区域因此与隧道区域自对准，并且掺杂物的横向扩散提供与漏极区域的电连续性。

公开(公告)号：EP0714099A1

公开(公告)日：1996-05-29

申请号：EP94830543.8

申请日：1994-11-24

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Baldi, Livio ,  Ricco', Bruno

IPC: G11C5/14 ,  G05F3/20

CPC classification number: G11C5/14 ,  G05F3/205

Abstract: An electronic circuit (30) integrated on a semiconductor in CMOS technology, being powered at a low supply voltage and having reduced power dissipation while in the off state, of the type which comprises at least one MOS or CMOS electronic device (2,3) formed on a semiconductor substrate (4) with a predetermined threshold voltage value (V T ), comprises at least one electronic switch (12,17) for connection of the substrate (4) to at least two different bias voltage references. This switch is controlled by a turn-off command signal to change the substrate (4) bias in the rest condition, and hence the threshold voltage (V T ) of the device upon the latter being turned off.

Abstract translation: 集成在CMOS技术的半导体，电子电路（30），在低电源电压被供电，并在关断状态具有降低的功耗的同时，其包括至少一个MOS或CMOS电子装置的类型（2,3） 形成在与规定的阈值电压（VT）的半导体基板（4）包括至少一个电子开关（12,17），用于在基板（4）的至少两个不同的偏置电压的引用的连接。 此开关由关断指令信号控制，以改变基片（4）偏压在静止状态，因此，阈值电压（VT）时后者设备被关断。

公开(公告)号：EP0704854A1

公开(公告)日：1996-04-03

申请号：EP94830471.2

申请日：1994-09-30

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Baldi, Livio

IPC: G11C29/00 ,  G06F11/10

CPC classification number: G06F11/1072 ,  G06F11/1064 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C29/00

Abstract: The present invention relates to a memory device and specifically the multilevel type with error check and correction function and having a data input (DI), a data output (DO) and an address input (AI) and being of the type comprising first memory means (DM) designed to be accessed by means of address for containing user data, second memory means (EM) for containing error data concerning said user data, a control logic (CL) designed to receive in the writing phase from said address input (AI) and said data input (DI) a writing address and user data respectively and to generate error data and to write said data in said first means (DM) and second means (EM) respectively and designed to receive in the reading phase from said address input (AI) a reading address and extract corresponding user data and error data and combine them to correct any errors and supply them to said data output (DO) and characterised in that said second means (EM) are the type designed to be accessed by means of content and said content for access corresponding to addresses of said first means (DM).

Abstract translation: 本发明涉及一种存储装置，特别具有错误检查和校正功能和具有数据输入（DI），数据输出（DO），并处理输入（AI）和为所述类型的，其包括第一存储装置，所述多级类型 （DM）设计成由地址的装置，用于包含用户数据，第二存储装置（EM），用于容纳关于errordata子所述用户数据，设计成接收在由所述地址输入端的写入阶段的控制逻辑（CL）被访问（AI ）和所述数据输入（DI）的写入地址和用户数据分别并产生错误数据，并分别写入在所述第一装置（DM）和第二装置（EM所述数据），并设计成接收在由所述地址读取相 输入（AI）的读取地址，并提取相应的用户数据和误差数据并将它们组合以纠正任何错误，并把它们提供到所述数据输出（DO）和DASS所述第二装置（EM）被类型设计成由被访问 C接通 ontent和所述内容访问对应的所述第一装置（DM）的地址。