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    Multiple instruction issue
    81.
    发明公开
    Multiple instruction issue 失效
    Mehrfachbefehlausgabe。

    公开(公告)号：EP0492968A2

    公开(公告)日：1992-07-01

    申请号：EP91311769.3

    申请日：1991-12-18

    Applicant: SGS-Thomson Microelectronics Limited

    Inventor： Azmoodeh, Saeid ,  Boffey, Peter Malcolm Keith ,  Forsyth, Richard Matthew ,  Parsons, Brian Jeremy

    IPC: G06F9/38

    CPC classification number: G06F9/3822 ,  G06F9/3824 ,  G06F9/3853 ,  G06F9/3885

    Abstract: Computer appratus includes an instruction execution unit (13) having a plurality of functional units (14,16) each arranged to execute at least part of an instruction and instruction issuing circuitry (10,12) for issuing simultaneously a group of separate compatible instructions to the execution unit (13) the circuitry (12) having means for classifying each instruction in dependence on the or each functional unit required for execution of that instruction and means for testing the classification of successive instructions and selecting a group which according to their classification are compatible for simultaneous issue to the execution unit (13) without conflicting demands on any function unit (14,16) in the execution unit.

    Abstract translation: 计算机设备包括具有多个功能单元（14,16）的指令执行单元（13），每个功能单元（14,16）被布置为执行指令和指令发布电路（10,12）的至少一部分，用于同时发出一组单独的兼容指令 执行单元（13）具有用于根据执行该指令所需的或每个功能单元对每个指令进行分类的装置，以及用于测试连续指令的分类的装置以及根据其分类选择的组 兼容于执行单元（13）的同时发布，而对执行单元中的任何功能单元（14,16）没有冲突的要求。

    Semiconductor chip packages
    82.
    发明公开
    Semiconductor chip packages 失效
    Halbleiterchippackungen。

    公开(公告)号：EP0430458A2

    公开(公告)日：1991-06-05

    申请号：EP90312152.3

    申请日：1990-11-06

    Applicant: SGS-Thomson Microelectronics Limited

    Inventor： Wakefield, Elwyn Paul Michael ,  Walker, Christopher Paul Hulme

    IPC: H01L23/50 ,  H01L25/10

    CPC classification number: H01L23/50 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor chip package (2) comprising at least one semiconductor chip disposed in a package and a plurality of first and second pins (18,20) extending from the package, which first pins are electrically connected to the at least one semiconductor chip and are adapted to conduct signals between the at least one semiconductor chip and external circuitry, the first pins being divided into a plurality of groups, each group representing a respective signal type, and which second pins are not electrically connected to the at least one semiconductor chip, the first pins of at least one group and the second pins being asymmetrically disposed along edges (14,16) of the package and the remaining groups of first pins being symmetrically disposed along edges of the package. The invention also provides a stacked module of the semiconductor chip packages.

    Abstract translation: 一种半导体芯片封装，包括设置在封装中的至少一个半导体芯片和从封装延伸的多个第一和第二引脚，该第一引脚电连接至该至少一个半导体芯片，并且适于在至少 一个半导体芯片和外部电路，所述第一引脚被分成多个组，每个组表示相应的信号类型，并且所述第二引脚不与所述至少一个半导体芯片电连接，所述至少一个组的第一引脚 并且所述第二销沿着所述封装的边缘不对称地设置，并且所述剩余的第一销的组沿着所述封装的边缘对称地设置。 本发明还提供了半导体芯片封装的堆叠模块。

    Memory cell
    83.
    发明公开
    Memory cell 失效
    Speicherzelle。

    公开(公告)号：EP0278587A2

    公开(公告)日：1988-08-17

    申请号：EP88300098.6

    申请日：1988-01-07

    Applicant: SGS-Thomson Microelectronics Limited

    Inventor： Campbell, Richard Norman ,  Edwards, Jonathan ,  Thompson, Michael Kevin

    IPC: H01L27/11 ,  G11C11/412

    CPC classification number: H01L27/1112 ,  G11C11/412

    Abstract: In a semi-conductor memory cell components are formed in regions separated from each other by one or more insulation layers (40) and first and second load resistors (20,22) and gate regions (70,72) of first and second cross-coupled driver field effect transistors (16,18) are formed in a first conductive layer (64) and the word line (36) and gate regions (66,68) of first and second transfer transistors (28,30) are formed in a second conductive layer (60).

    Abstract translation: 在半导体存储单元中，元件通过一个或多个绝缘层（40）和第一和第二横截面的第一和第二负载电阻（20,22）和栅极区（70,72）彼此分开形成， 耦合驱动器场效应晶体管（16,18）形成在第一导电层（64）中，并且第一和第二转移晶体管（28,30）的字线（36）和栅极区域（66,68）形成在 第二导电层（60）。

    A METHOD FOR REMOTELY CONTROLLING A PLURALITY OF APPARATUS USING A SINGLE REMOTE CONTROL DEVICE
    84.
    发明公开
    A METHOD FOR REMOTELY CONTROLLING A PLURALITY OF APPARATUS USING A SINGLE REMOTE CONTROL DEVICE 失效
    方法通过一个遥控器控制多台设备的远程控制

    公开(公告)号：EP0917767A1

    公开(公告)日：1999-05-26

    申请号：EP98913948.0

    申请日：1998-03-31

    Applicant: SGS-Thomson Microelectronics Limited

    Inventor： HULME, Peter, John

    IPC: H04B1

    CPC classification number: H04B1/205

    Abstract: The present invention relates to a method of controlling one or more second apparatus from a first apparatus, which is responsive to first control signals from a first remote control device. The characteristic steps of the method comprise: providing the first remote control with additional operational functions, and corresponding third control signals, that correspond to functions of said second apparatus; receiving and storing in said first apparatus, as part of an initialisation procedure, second control signals that have corresponding third control signals, said second control signals being stored as second reference control signals in a storage medium; receiving said third control signals from said first remote control; receiving said second reference control signals from said storage medium; comparing said third control signals and said second reference control signals; and controlling, by means of said second reference control signals, said second apparatus, via said first apparatus, when said third control signals and said second reference control signals equal each other.

    A cache coherency mechanism
    85.
    发明公开
    A cache coherency mechanism 失效
    Cachespeicherkohärenzmechanismus

    公开(公告)号：EP0863464A1

    公开(公告)日：1998-09-09

    申请号：EP98301617.1

    申请日：1998-03-04

    Applicant: SGS-Thomson Microelectronics Limited

    Inventor： Barnaby, Catherine ,  Fel, Bruno ,  Farrall, Glen

    IPC: G06F12/08

    CPC classification number: G06F9/30047 ,  G06F12/0837 ,  G06F12/0891

    Abstract: A computer system has a processor, a cache and a main memory. A cache coherency mechanism ensures that the contents of the cache are coherent with respect to main memory by the provision of cache coherency instructions which each specify: 1) an operation to be executed on the contents of a location in the cache; and 2) an address in main memory. The operation is executed for the contents of the location in the cache which could be filled by an access to that address in main memory if the executing process normally has access to that address in main memory, regardless of whether or not the contents of the specified address in main memory are held at that location in the cache.
    This provides an extra degree of freedom because it is not necessary for the cache coherency operation to be requested in respect of a particular address stored in the cache. The instruction can specify any address which would map onto that cache location.

    Abstract translation: 计算机系统具有处理器，高速缓存和主存储器。 高速缓存一致性机制通过提供高速缓存一致性指令来确保高速缓存的内容与主存储器一致，每个指令分别指定：1）对高速缓存中的位置的内容执行的操作; 和2）主存储器中的地址。 如果执行过程通常可以访问主存储器中的该地址，则可以通过对主存储器中的该地址的访问来填充缓存中的位置的内容的操作，而不管指定的内容 主存储器中的地址保存在缓存中的该位置。 这提供了额外的自由度，因为关于存储在高速缓存中的特定地址不需要缓存一致性操作被请求。 该指令可以指定映射到该缓存位置的任何地址。

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