公开(公告)号：JPH10209396A

公开(公告)日：1998-08-07

申请号：JP1196397

申请日：1997-01-07

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SHI WAY SAN

IPC: H01L21/8242 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12

Abstract: PROBLEM TO BE SOLVED: To provide a SOIDRAM which is high in versatility when a capacitor structure is designed, and a method for forming the structure. SOLUTION: A silicon-on-insulator(SOI) DRAM is possessed of a buried oxide layer coated with a thin crystalline silicon layer on the surface of a silicon main body substrate 10. A field oxide region is formed so as to come into contact with the buried oxide layer through the intermediary of the thin crystalline silicon surface layer. A gate oxide layer, a gate electrode 18, and a source/drain region 24 for the transfer FET of the DRAM are formed inside and on the thin crystalline silicon surface layer in an active region between field oxide regions. A groove is cut in one of the source/drain regions 24 of the transfer FETs. A doped polysilicon layer is provided conforming to the groove and patterned to serve as, at least, a part of the base electrode of a storage capacitor for the DRAM. The base electrode 32 is coated with a thin dielectric layer, and an upper electrode 36 of doped polysilicon is provided. It is preferable that a groove for a base capacitor electrode may be provided in a silicon main body penetrating through the buried oxide layer.

公开(公告)号：JPH1079486A

公开(公告)日：1998-03-24

申请号：JP508797

申请日：1997-01-14

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHAO FANG-CHING

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method for semiconductor memory elements having wide-area tree-type capacitors for storing of data-representing charges. SOLUTION: On an Si substrate 10 a field oxide film and gate oxide film are formed. By the CVD a poly-Si film is formed, W is vacuum-evaporated and heat treated to form a low-resistance silicide film, which is then patterned to form gate electrodes WL1-WL4. Using these electrodes as a mask, P ions are implanted and diffused to form drain regions 16a, 16b and source regions 18a, 18b. A BPSG film 20 and SiN etching protection layer 22 are formed. A first insulation layer, poly-Si layers 28a, 28b and a second insulation layer are formed by the CVD. The poly-Si layer top is treated by CMP to separate into numerous independent sections. Each of the above layers is etched to form connecting holes up to the drain/source region, and poly-Si 34a, 34b are filled in the connecting holes. Tree-type memory electrodes for DRAM capacitors are formed, and dielectric counter films 36a, 36b and poly-Si facing electrodes 38 are vacuum-evaporated to complete the element.

公开(公告)号：JPH1079485A

公开(公告)日：1998-03-24

申请号：JP508697

申请日：1997-01-14

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHAO FANG-CHING

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To widen a charge storage area by widening the surface of a branch conductive layer connected to a trunk conductive layer connected to a drain region of a transfer transistor and by forming an overlay conductive layer on a dielectric layer formed on an exposed face of the both of the conductive layers. SOLUTION: Trunk-polysilicon layers 34a, 34b forming a tree-type storage electrode for a capacitor of a DRAM are electrically connected to drain regions 16a, 16b of a transfer transistor in the DRAM, respectively. The cross section for each of branch polysilicon layers 28a, 28b is almost an L-shape and horizontal cross sections are generally electrically in contact with the trunk-polysilicon layers 34a, 34b. Dielectric film 36a, 36b are formed on the tree-type storage electrodes 34a, 28a and the three-type storage electrode 34b, 28b, respectively. A polysilicon counter electrode 38 facing the storage electrodes 34a, 28a and 34b, 28b is formed on the dielectric films 36a, 36b.

公开(公告)号：JPH1079477A

公开(公告)日：1998-03-24

申请号：JP9118197

申请日：1997-04-09

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHAO FANG-CHING

IPC: H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To increase a charge storage area by providing a transfer transistor and a storage capacitor which are electrically connected to a source/drain region of the transfer transistor. SOLUTION: Hollow trunk-shaped polysilicon layers 46a and 46b are formed at an opening by depositing a polysilicon layer by evaporation on a substrate 10, and furthermore, the substrate 10 is etched back. The polysilicon layers 46a and 46b respectively have inner surfaces 47a and 47b in direct contact with polysilicon layers 26a and 40a, and 20b and 40b. The polysilicon layers 26a, 40a and 46a form a storage electrode 49a, and the polysilicon layers 26b, 40b and 46b form a storage electrode 49b. Dielectric layers 48a and 48b are respectively formed on the exposed surfaces of the storage electrodes 49a and 49b. next, polysilicon oppositely located electrodes 50 are formed on the surfaces of the dielectric layers 48a and 48b.

公开(公告)号：JPH1012737A

公开(公告)日：1998-01-16

申请号：JP3937697

申请日：1997-02-24

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SON KISHU ,  KYU SEITEN ,  SAI MEIKO

IPC: C23C16/04 ,  C23C16/20 ,  H01L21/28 ,  H01L21/285 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To provide a connection body for electric connection which has no break and high reliability for a semiconductor IC device, and its formation. SOLUTION: The aluminum plug 28 is formed through a process for forming a semiconductor constituent element on a substrate 20 which has an insulating layer 24, having a contact opening 26 for exposing a conductive area 22 of the semiconductor constituent element, formed on the top surface, a process for vacuum heat annealing of the substrate 20, and a process for connecting the conductive area 22 in the contact opening 26 on the top surface of the substrate and depositing aluminum selectively not on the top surface of the insulating layer 24, but on the exposed conductive area 22 in a CVD process that uses DMEAA (dimemethyl ether amine allene) as a precursor and is carried out at substrate temperature with deposit selectivity.

公开(公告)号：JPH09269854A

公开(公告)日：1997-10-14

申请号：JP14748296

申请日：1996-06-10

Applicant: UNITED MICROELECTRONICS CORP

Inventor： ROGAA CHIEN ,  NEIRU TAI ,  TOMII CHIEN ,  UESURII JIEN

IPC: G06F1/32 ,  G06F1/26

Abstract: PROBLEM TO BE SOLVED: To reduce power and to adjust a device to a standard by setting a system to a power cut mode and setting it to return to a regular operation mode in response to an external trigger signal under an appropriate situation. SOLUTION: When a central processing unit 10 executes a meaningless DO loop, the system starts a special service program for saving necessary data, a notice for power-cutting the central processing unit 10 is given to a power controller 20 and the central processing unit 10 becomes a power cut state for reducing power consumption. When a new event is started, a trigger controller 30 decides it or receives the external trigger signal. A starting resetting signal 16 is transmitted to the power controller 20 is response to the trigger signal, the power controller 20 is triggered by the signal and the power of the central processing unit 10 is restored. The power of the central processing unit 10 is supplied, necessary data is restored and the internal program is executed in response to the new event.

公开(公告)号：JPH0982436A

公开(公告)日：1997-03-28

申请号：JP23186195

申请日：1995-09-08

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SHINNFUI CHIYAN

IPC: H01R33/76 ,  H01L23/32 ,  H05K7/10

Abstract: PROBLEM TO BE SOLVED: To secure a pin socket to a circuit board for mounting an integrated circuit. SOLUTION: This socket is formed out of a base and a plurality of socket pins 15 arranged around the base for electrical connection to the part (pins) of an integrated circuit. Furthermore, each of the socket pin 15 is provided with a connection part 17 for the convenience of soldering an additional component, or generating a shortcircuit with a part of other pins 15.

公开(公告)号：JPH08124421A

公开(公告)日：1996-05-17

申请号：JP25563994

申请日：1994-10-20

Applicant: UNITED MICROELECTRONICS CORP

Inventor： NENGU FUSHINGU RU ,  NINGU YANGU ,  JIEI SHII DENGU ,  DEITSUKU RIYAO

IPC: H05K1/09 ,  C09J9/02 ,  C09J11/04 ,  H01B1/00 ,  H01B1/22 ,  H01B5/00 ,  H01B5/16 ,  H01R11/01 ,  H05K3/32

Abstract: PURPOSE: To provide an adhesive for connecting a circuit member having a conductive terminal to a substrate having a mounting surface equipped with a plurality of tracks on its side part and to provide a connecting method which can secure reliable electric connection by making a conductive terminal adhere steadfastly to a necessary position. CONSTITUTION: A conductive adhesive comprises at least 10 wt.% of compressed hollow conductive particles dispersed in a non-conductive resin. A connecting method consists of the following five steps of: (a) applying the above-mentioned adhesive to a surface of a substrate on which a circuit member is to be mounted; (b) mounting a conductive terminal of the circuit member on a pre-selected conductive passage among passages, adjusting the terminal vertically to the passage with the help of adhesive; (c) applying a magnetic field vertically to a complex consisting of a combination of a mounting surface, the adhesive, and the circuit member and collecting conductive particles between the conductive terminal and the passage; (d) applying a pressure to the circuit member under the existence of the magnetic field, so that a part of adhesive is made to be squeezed from between the conductive terminal and the passage; and (e) hardening the adhesive.

公开(公告)号：JPH08123412A

公开(公告)日：1996-05-17

申请号：JP25859294

申请日：1994-10-24

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHIMAO FUAN

IPC: G10H7/02 ,  G10H1/057 ,  G10K15/04 ,  G10L21/02 ,  H03M1/74 ,  G10L3/02

Abstract: PURPOSE: To provide an analog synthesized musical sound inverter with the simple structure at a low cost by proportioning an output value of the converting current to a current change of the product of envelope and tone, and feeding the current, which compensates the envelop generating unit with each other. CONSTITUTION: An envelope current generating unit 30 and a tone current generating unit 40 are connected to a right side of a referential current generating unit 20 in order. A direct current drift compensating unit 70 is formed by connecting a compensating current generating unit 50 and a current amplifying unit 60 in series. In this case, total current variable (Ib1+Ib2) of the compensating current generating unit 50 and the envelope current generating unit 30 is constant. Namely, when one of current variable is increased, the other current variable is reduced. The current amplifying unit 60 following to the compensating current generating unit 50 uses an intermediate value of tone. The output signal value I0 of an analog converter 10 is in proportion to the product of tone T and envelope E, and a D/A converter, which can achieve the effect by multiplying the tone signal and the envelope signal, is formed.

公开(公告)号：JP2010085470A

公开(公告)日：2010-04-15

申请号：JP2008251641

申请日：2008-09-29

Applicant: United Microelectronics Corp ,  聯華電子股▲分▼有限公司

Inventor： YANG YU SHIANG ,  WU TE-HUNG ,  CHENG YUNG-FENG ,  YANG CHUEN-HUEI ,  HUANG HSIANG-YUN ,  KUO HUI-FANG ,  KUO SHIH-MING ,  CHEN LUN-HUNG

IPC: G03F1/36 ,  G03F1/68 ,  G03F1/70

Abstract: PROBLEM TO BE SOLVED: To provide a method for selectively correcting a layout pattern. SOLUTION: A first layout pattern including at least a first group and a second group is provided. Each of the first group and the second group includes a plurality of members. All members in the first group and the second group are individually subjected to a simulation process and a correction process to obtain a corrected first group and a corrected second group. The corrected first group and the corrected second group are verified whether the groups reach the target or not. After verification, a layout pattern including the corrected first group reaching the target and the corrected second group reaching the target is output. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于选择性地校正布局图案的方法。 提供了包括至少第一组和第二组的第一布局图案。 第一组和第二组中的每一个包括多个构件。 第一组和第二组中的所有成员分别经受模拟处理和校正处理，以获得校正的第一组和校正的第二组。 验证校正的第一组和校正的第二组是否到达目标。 在验证之后，输出包括到达目标的校正的第一组和到达目标的校正的第二组的布局模式。 版权所有（C）2010，JPO＆INPIT