公开(公告)号：KR100609996B1

公开(公告)日：2006-08-09

申请号：KR1019990037797

申请日：1999-09-07

Applicant: 삼성전자주식회사

Inventor： 윤중림 ,  김영욱

IPC: H01L21/3205

Abstract: 본 발명은 반도체소자의 제조방법을 게시한다. 이에 의하면, 층간절연막의 다마신(damascene) 구조의 홈부들에만 채워진 구리배선들을 제외한 그 외측의 층간절연막 상에 감광막의 패턴을 형성한 후 감광막의 패턴과 구리배선들 상에 캐핑층을 함께 적층하고 이를 기계화학적 연마공정을 이용하여 구리배선들 외측의 층간절연막 상에 있는 캐핑층을 완전히 제거하고 구리배선들 상에만 캐핑층을 남긴다.
따라서, 본 발명은 구리배선들 상에 캐핑층을 형성하면서도 이들 사이의 층간절연막 상에 캐핑층을 전혀 존재하지 않게 하여 구리배선들 사이의 프린지(fringe) 커패시턴스를 줄이고 나아가 RC지연시간을 단축하여 로직소자의 고속화를 이룬다.

Abstract translation: 本发明公开了一种制造半导体器件的方法。 利用这种结构，在层间绝缘膜和饮用水（镶嵌）到感光膜图案和铜布线形成在其外侧填充结构的仅槽部上层叠有覆盖层的除铜布线以外的层间绝缘膜中的光致抗蚀剂图案之后 这是通过使用机械化学抛光工艺来完成的，以完全去除铜互连外部的层间绝缘膜上的覆盖层并仅将覆盖层留在铜互连上。

公开(公告)号：KR100492972B1

公开(公告)日：2005-06-07

申请号：KR1020030002460

申请日：2003-01-14

Applicant: 삼성전자주식회사

Inventor： 김영욱

IPC: H04W8/26 ,  H04W8/28 ,  H04W8/06

Abstract: 본 발명은 이동통신 단말기에게 각각 서로 다른 전화번호를 부여하는 적어도 두 개 이상의 서로 다른 사업자 망들을 포함하는 이동통신 시스템에서 상기 이동통신 단말기가 이동 시, 상기 이동통신 단말의 이동전화번호를 갱신하는 방법에 있어서, 상기 이동통신 단말기가 현재 자신이 위치하고 있는 사업자 망의 네트워크로 위치 등록을 요구하고, 상기 이동통신 단말기가 상기 네트워크로부터 현재 자신이 위치하고 있는 사업자 망에서 제공하는 이동전화번호를 수신하고, 상기 이동통신 단말기가 상기 수신한 이동전화번호와 기존에 상기 이동통신 단말기 내부에 저장되어 있는 이동전화번호가 동일한 지의 여부를 판단하고, 상기 수신한 이동전화번호와 상기 저장되어 있는 이동전화번호가 동일하지 않을 시, 상기 이동통신 단말기는 상기 수신한 � �동전화번호를 자신의 이동전화번호로 갱신하는 방법을 제안한다.

公开(公告)号：KR1020040065480A

公开(公告)日：2004-07-22

申请号：KR1020030002460

申请日：2003-01-14

Applicant: 삼성전자주식회사

Inventor： 김영욱

IPC: H04W8/26 ,  H04W8/28 ,  H04W8/06

Abstract: PURPOSE: A method for updating an MDN(Mobile Directory Number) of a mobile communication terminal in a mobile communication system is provided to enable a mobile communication terminal to update a received MDN as a self MDN if the received MDN is not identical with a stored MDN, so that a user does not have to manually input the MDN. CONSTITUTION: An MS(200) periodically transmits a location registration message to a BSC(210)(40). The BSC(210) transmits a location registration update request message to an MSC/VLR(220)(41). The MSC/VLR(220) transmits a location registration notification message to an HLR(230)(42). The HLR(230) transmits a location registration notification return result message(43). The MSC/VLR(220) transmits a location registration update response message to the BSC(210)(44). The BSC(210) transmits a location registration response message including an MDN(45). If the received MDN is identical with a stored MDN, the MS(200) updates with the received MDN.

Abstract translation: 目的：提供一种用于更新移动通信系统中的移动通信终端的MDN（移动目录号码）的方法，以使移动通信终端能够将所接收的MDN作为自身MDN更新，如果所接收的MDN与所存储的MDN不相同 MDN，使用户不必手动输入MDN。 构成：MS（200）周期性地向BSC（210）（40）发送位置登记消息。 BSC（210）向MSC / VLR（220）发送位置登记更新请求消息（41）。 MSC / VLR（220）向HLR（230）发送位置登记通知消息（42）。 HLR（230）发送位置登记通知返回结果消息（43）。 MSC / VLR（220）向BSC（210）发送位置登记更新响应消息（44）。 BSC（210）发送包括MDN（45）的位置登记响应消息。 如果所接收的MDN与所存储的MDN相同，则MS（200）随接收的MDN更新。

公开(公告)号：KR1020040060441A

公开(公告)日：2004-07-06

申请号：KR1020020087238

申请日：2002-12-30

Applicant: 삼성전자주식회사

Inventor： 오명환 ,  오창봉 ,  김영욱 ,  강희성 ,  유혁주 ,  고영건

IPC: H01L21/336

CPC classification number: H01L21/28176 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/6659

Abstract: PURPOSE: A method for fabricating a semiconductor device having a gate pattern is provided to cure damage in an etch process for forming a gate pattern by performing a curing process such as an oxygen annealing process and a re-oxidation process. CONSTITUTION: A gate insulating layer(22) is formed on an upper surface of a semiconductor substrate(20). A gate conductive layer(24) is deposited on the upper surface of the semiconductor substrate including the gate insulating layer. A gate pattern is formed by etching the gate conductive layer. A buffer layer(26) is formed on the gate pattern in order not to expose the gate insulating layer. A curing process is performed to remove the damage generated from the etch process for forming the gate pattern.

Abstract translation: 目的：提供一种用于制造具有栅极图案的半导体器件的方法，以通过执行诸如氧退火工艺和再氧化工艺的固化工艺在用于形成栅极图案的蚀刻工艺中固化损伤。 构成：在半导体衬底（20）的上表面上形成栅极绝缘层（22）。 栅极导电层（24）沉积在包括栅极绝缘层的半导体衬底的上表面上。 通过蚀刻栅极导电层形成栅极图案。 为了不露出栅极绝缘层，在栅极图案上形成缓冲层（26）。 执行固化过程以消除由用于形成栅极图案的蚀刻工艺产生的损伤。

公开(公告)号：KR1020040038546A

公开(公告)日：2004-05-08

申请号：KR1020020067545

申请日：2002-11-01

Applicant: 삼성전자주식회사

Inventor： 김경수 ,  김영욱 ,  오창봉 ,  강희성 ,  유혁주

IPC: H01L21/336

CPC classification number: H01L29/42368 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/31116 ,  H01L21/31604 ,  H01L21/31616 ,  H01L21/3185 ,  H01L27/11 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: PURPOSE: A method for fabricating a gate dielectric layer with a multiple thickness in a semiconductor device is provided to embody high thickness uniformity by precisely controlling the thickness of the gate dielectric layer when the gate dielectric layer with the multiple thickness is formed on the same substrate. CONSTITUTION: The first dielectric layer(210) is formed on a semiconductor substrate(100). The second dielectric layer(310) is formed on the first dielectric layer, made of a dielectric material different from that of the first dielectric layer. A part of the second dielectric layer is eliminated to selectively expose a portion of the first dielectric layer under the second dielectric layer. A gate dielectric layer is formed which includes a relatively thick portion composed of the first dielectric layer and the residual second dielectric layer and a relatively thin portion composed of the exposed first dielectric layer.

Abstract translation: 目的：提供一种用于在半导体器件中制造具有多个厚度的栅极电介质层的方法，以在具有多个厚度的栅极介电层形成在同一衬底上时精确地控制栅极电介质层的厚度来实现高厚度均匀性 。 构成：第一电介质层（210）形成在半导体衬底（100）上。 第二电介质层（310）形成在由与第一电介质层不同的电介质材料制成的第一电介质层上。 消除第二电介质层的一部分以选择性地暴露第二电介质层下的第一电介质层的一部分。 形成栅极电介质层，其包括由第一电介质层和残留的第二电介质层组成的相对较厚的部分，以及由暴露的第一介电层组成的相对薄的部分。

公开(公告)号：KR100344220B1

公开(公告)日：2002-07-19

申请号：KR1019990045495

申请日：1999-10-20

Applicant: 삼성전자주식회사

Inventor： 고영건 ,  김병선 ,  김영욱

IPC: H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/84

Abstract: 다이오드나웰 저항등으로사용되는확산영역상에자기정합적으로실리사이드층형성시, 스페이서를이용하여실리사이드층이형성되어질부분을특정범위내로제한시켜주므로써, "실리사이드층측면 ~ 확산영역측면"까지의거리(ℓ2)를기존보다충분히크게확보할수 있도록하여, 확산영역측면에서발생되는정션리키지전류를최소화할수 있도록한 SOI 구조를갖는반도체소자및 그제조방법이개시된다. 상기반도체소자는, ①다이오드(혹은웰 저항)로사용되는확산영역을스페이서를이용하여농도구배가다른이중정션구조(예컨대, P-층이 P+층을감싸는구조나혹은 N-층이 N+층을감싸는구조)로가져가되, 실리사이드층이고농도불순물층즉, P+층이나 N+층의표면에만형성되도록설계되거나또는② 다이오드(혹은웰 저항)로사용되는확산영역을단일정션구조로가져가되, 스페이서에의해확산영역상에서실리사이드층이형성될범위가제한되도록설계된다.

公开(公告)号：KR1020010037796A

公开(公告)日：2001-05-15

申请号：KR1019990045495

申请日：1999-10-20

Applicant: 삼성전자주식회사

Inventor： 고영건 ,  김병선 ,  김영욱

IPC: H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/84

Abstract: PURPOSE: A semiconductor device having a silicon-on-insulator(SOI) structure is provided to minimize a junction leakage current generated at a side surface of a diffusion region, by guaranteeing a distance from a side surface of a silicide layer to a side surface of the diffusion region, the distance being longer than that of a conventional technology. CONSTITUTION: A surface silicon layer(100c) is formed on a semiconductor substrate by interposing an insulating layer(100b). A concave groove part is formed by etching the surface silicon layer and the insulating layer to expose a predetermined part. A spacer(124a) is formed on both sidewalls of the concave groove part. A diode diffusion region is formed in the substrate of a lower surface of the concave groove part. A silicide layer(138) is formed in the diode diffusion region between the spacers.

Abstract translation: 目的：提供一种具有绝缘体上硅（SOI）结构的半导体器件，用于通过保证从硅化物层的侧表面到侧表面的距离来最小化在扩散区的侧表面处产生的结漏电流 的扩散区域，其距离比传统技术的长。 构成：通过插入绝缘层（100b）在半导体衬底上形成表面硅层（100c）。 通过蚀刻表面硅层和绝缘层来形成凹槽部分以暴露预定部分。 在凹槽部分的两个侧壁上形成间隔物（124a）。 在凹槽部的下表面的基板上形成二极管扩散区域。 在间隔物之间​​的二极管扩散区域中形成硅化物层（138）。

公开(公告)号：KR1020010027434A

公开(公告)日：2001-04-06

申请号：KR1019990039170

申请日：1999-09-14

Applicant: 삼성전자주식회사

Inventor： 고영건 ,  김병선 ,  김영욱

IPC: H01L21/76

Abstract: PURPOSE: An isolation method for a semiconductor device of a silicon-on-insulator(SOI) type is provided to attain good gate oxide characteristics and good transistor characteristics. CONSTITUTION: In the method, an SOI substrate has a buried oxide layer(101) and a surface silicon layer(102) formed on a silicon substrate(100). The first insulating layer(103) and the second insulating layer are then formed on the SOI substrate and etched to form an opening therein. Next, the surface silicon layer(102) is etched through the opening in the insulating layers(103) to form a trench therein. Thereafter, nitrogen ions are implanted into the etched silicon layer(102) and the exposed oxide layer(101) to form a nitrogen-implanted silicon layer(152). Then, a thermal oxide layer(160) is formed on a sidewall of the surface silicon layer(102). Next, the third insulating layer is formed enough to fill the trench in the surface silicon layer(102) and then polished or etched. Therefore, the third insulating layer is removed together with the second insulating layer, but remains in the trench(180).

Abstract translation: 目的：提供绝缘体上硅（SOI）型半导体器件的隔离方法，以获得良好的栅极氧化物特性和良好的晶体管特性。 构成：在该方法中，SOI衬底具有形成在硅衬底（100）上的掩埋氧化物层（101）和表面硅层（102）。 然后在SOI衬底上形成第一绝缘层（103）和第二绝缘层，并在其中蚀刻以形成开口。 接下来，通过绝缘层（103）中的开口蚀刻表面硅层（102），以在其中形成沟槽。 此后，将氮离子注入到蚀刻硅层（102）和暴露的氧化物层（101）中以形成氮注入硅层（152）。 然后，在表面硅层（102）的侧壁上形成热氧化层（160）。 接下来，第三绝缘层被形成为足以填充表面硅层（102）中的沟槽，然后被抛光或蚀刻。 因此，第三绝缘层与第二绝缘层一起被去除，但保留在沟槽（180）中。

公开(公告)号：KR1020010026464A

公开(公告)日：2001-04-06

申请号：KR1019990037797

申请日：1999-09-07

Applicant: 삼성전자주식회사

Inventor： 윤중림 ,  김영욱

IPC: H01L21/3205

Abstract: PURPOSE: A method for manufacturing a semiconductor device is provided to reduce fringe capacitance and to shorten resistor-capacitor(RC) delay time, by forming a capping layer on copper interconnections while preventing the capping layer on an interlayer dielectric between the copper interconnections. CONSTITUTION: The first conductor(11) is formed on a semiconductor substrate. An interlayer dielectric(13) is formed on the semiconductor substrate, exposing a partial region of the first conductor and having groove parts separated from each other by a predetermined interval where the groove parts have a damascene structure. After a barrier layer(17) is formed on the interlayer dielectric inside the exposed first conductor and the grooves to prevent a copper diffusion to the first conductor, copper interconnections(21) filled in the grooves are formed. A capping layer(27) is selectively formed on the copper interconnection to prevent a copper diffusion from an upper surface of the copper interconnections.

Abstract translation: 目的：提供一种用于制造半导体器件的方法，以通过在铜互连上形成覆盖层同时防止铜互连之间的层间电介质上的覆盖层，来减少边缘电容并缩短电阻 - 电容（RC）延迟时间。 构成：第一导体（11）形成在半导体衬底上。 在半导体衬底上形成层间电介质（13），暴露出第一导体的部分区域，并且将槽部分彼此隔开预定的间隔，其中沟槽部分具有镶嵌结构。 在暴露的第一导体和沟槽之间的层间电介质上形成阻挡层（17），以防止铜扩散到第一导体，形成填充在槽中的铜互连（21）。 在铜互连上选择性地形成覆盖层（27），以防止铜从铜互连的上表面扩散。

公开(公告)号：KR100270955B1

公开(公告)日：2000-12-01

申请号：KR1019980008792

申请日：1998-03-16

Applicant: 삼성전자주식회사

Inventor： 이경태 ,  김영욱

IPC: H01L21/28

CPC classification number: H01L21/76838

Abstract: PURPOSE: A method for manufacturing a semiconductor device is provided to eliminate a process defect generated in forming a fine contact hole of via hole, by making the contact or via hole have a vertically-stacked structure by using a multistep etch process. CONSTITUTION: The first interlayer dielectric(210) having the first contact hole(h1) is formed on a semiconductor substrate(s) having a conductive pattern. The first conductive plug(214) is formed in the first contact hole. The second interlayer dielectric(216) having the second contact hole(h2) is formed on the first interlayer dielectric to be connected to the first contact hole as one body. The second conductive plug(218) is formed in the second contact hole. A metal interconnection(220) is formed in a predetermined portion of the second interlayer dielectric to be connected to the second conductive plug.

Abstract translation: 目的：提供一种制造半导体器件的方法，以通过使用多步蚀刻工艺使接触或通孔具有垂直堆叠的结构来消除在形成通孔的细小接触孔时产生的工艺缺陷。 构成：具有第一接触孔（h1）的第一层间电介质（210）形成在具有导电图案的半导体衬底上。 第一导电插塞（214）形成在第一接触孔中。 具有第二接触孔（h2）的第二层间电介质（216）形成在作为一体连接到第一接触孔的第一层间电介质上。 第二导电插塞（218）形成在第二接触孔中。 金属互连（220）形成在第二层间电介质的预定部分中以连接到第二导电插塞。