公开(公告)号：KR1020110015269A

公开(公告)日：2011-02-15

申请号：KR1020090072906

申请日：2009-08-07

Applicant: 삼성전자주식회사

Inventor： 김용준 ,  김재홍 ,  이기준

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/24 ,  G11C16/08

CPC classification number: G11C11/5628 ,  G11C7/1012 ,  G11C11/5642 ,  G11C2211/5647

Abstract: PURPOSE: A memory system and a programming method thereof are provided to reduce a coupling effect by modulating data to be programmed. CONSTITUTION: A nonvolatile memory device(120) stores modulation data inputted from a memory controller(140) in a writing operation. A page(123) includes a user data area(1231) and a spare area(1232). The user data area stores modulation data. The spare area stores information related to the modulation of the data. An input and output circuit(124) temporarily stores the modulation data inputted in the writing operation in a corresponding page for programming.

Abstract translation: 目的：提供存储器系统及其编程方法，以通过调制要编程的数据来减少耦合效应。 构成：非易失性存储装置（120）在写入操作中存储从存储器控制器（140）输入的调制数据。 页面（123）包括用户数据区（1231）和备用区（1232）。 用户数据区存储调制数据。 备用区域存储与数据的调制有关的信息。 输入和输出电路（124）将在写入操作中输入的调制数据临时存储在相应的编程页面中。

公开(公告)号：KR1020100127406A

公开(公告)日：2010-12-06

申请号：KR1020090045838

申请日：2009-05-26

Applicant: 삼성전자주식회사

Inventor： 김용준 ,  은희석 ,  유한웅 ,  김재홍 ,  손홍락

IPC: G11C16/26 ,  G11C16/34

CPC classification number: G11C16/26 ,  G06F11/1048 ,  G11C11/5642 ,  G11C16/0483 ,  G11C29/00

Abstract: PURPOSE: A storing apparatus and a reading method of the same are provided to optimize a reading operation by setting a reading level based on a filtered distribution of the reading operation. CONSTITUTION: A storing unit(12) stores data. An error controlling unit(14) corrects the errors of data read from the strong unit based on at least one reading level. The error controlling unit outputs a error correcting failure signal(ECF). A reading level controlling unit(16) responds to the error correcting failure signal and sets a new reading level. The reading level controlling unit includes a filter(17) in order to filter the measured distribution of memory cells from the storing unit.

Abstract translation: 目的：提供存储装置及其读取方法，以通过基于读取操作的滤波分布设置读取级别来优化读取操作。 构成：存储单元（12）存储数据。 错误控制单元（14）基于至少一个读取级别来校正从强单元读取的数据的错误。 误差控制单元输出纠错失败信号（ECF）。 读取电平控制单元（16）响应纠错失败信号并设置新的读取电平。 读取电平控制单元包括滤波器（17），以便从存储单元滤出测量的存储单元分布。

公开(公告)号：KR1020100124892A

公开(公告)日：2010-11-30

申请号：KR1020090043825

申请日：2009-05-20

Applicant: 삼성전자주식회사

Inventor： 김용준 ,  김재홍 ,  공준진 ,  손홍락 ,  송승환

IPC: G11C16/26 ,  G11C16/30

CPC classification number: G11C11/5642 ,  G11C29/00 ,  G11C2211/5634 ,  G11C16/26

Abstract: PURPOSE: A method for setting a read voltage is provided to minimize the number of a bit in which an error is generated by compensating an offset. CONSTITUTION: A first voltage distribution corresponds to a first voltage-state. A second voltage distribution corresponds to a second voltage state. A read error probability value use a read voltage as a variable. The read error probability value is calculated based on the first and second voltage distribution and control the read voltage to be minimum.

Abstract translation: 目的：提供一种用于设置读取电压的方法，以通过补偿偏移来最小化产生错误的位的数量。 构成：第一电压分布对应于第一电压状态。 第二电压分布对应于第二电压状态。 读错误概率值使用读取电压作为变量。 基于第一和第二电压分布计算读误差概率值，并将读电压控制为最小。

公开(公告)号：KR1020100101895A

公开(公告)日：2010-09-20

申请号：KR1020090020327

申请日：2009-03-10

Applicant: 삼성전자주식회사

Inventor： 김재홍 ,  공준진 ,  김용준

IPC: G06F12/06 ,  G06F13/14 ,  G06F9/06

CPC classification number: G06F11/10 ,  H03M13/1102 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/23 ,  H03M13/2707 ,  H03M13/271 ,  H03M13/2906 ,  H03M13/2909 ,  H03M13/2927 ,  H03M13/2957

Abstract: PURPOSE: A data processing system having concatenated coding and decoding structure is provided to improve the reliability characteristic of the data processing system through an effective concatenation way of inner encoders and outer encoders. CONSTITUTION: A memory channel(200) stores data. A concatenated encoder(100) encodes the data, data that will be transmitted to the memory channel. The encoder comprises an outer encoder(120) and an inner encoder(140). The outer encoder generates outer codewords by encoding the data that will be transmitted to the memory channel. The inner encoder generates a plurality of inner codewords by encoding the outer codewords.

Abstract translation: 目的：提供具有级联编码和解码结构的数据处理系统，通过内编码器和外编码器的有效连接方式提高数据处理系统的可靠性。 构成：存储信道（200）存储数据。 级联编码器（100）对将被发送到存储器通道的数据进行编码。 编码器包括外部编码器（120）和内部编码器（140）。 外部编码器通过对将被发送到存储器通道的数据进行编码来生成外部码字。 内部编码器通过对外部码字进行编码来生成多个内部码字。

公开(公告)号：KR1020100039647A

公开(公告)日：2010-04-16

申请号：KR1020080098694

申请日：2008-10-08

Applicant: 삼성전자주식회사

Inventor： 김용준 ,  공준진 ,  김재홍 ,  조경래

IPC: G06F12/00 ,  G06F9/00 ,  G06F7/58

CPC classification number: G06F11/1008

Abstract: PURPOSE: A data storage device and a data storage system with the same are provided to increasing randomness by selectively randomizing input data. CONSTITUTION: A controller(20) decides characteristics of first input data. The controller outputs a first control signal based on the decided input data of the first input data. A randomizer(10) selectively randomizes the first input data in response to the first control signal outputted from the controller. An error correction encoder(50) generates the first input data by encoding second input data to error correction codes. A de-randomizer(30) performs reverse randomization of read data which is read in response to a read command from a host.

Abstract translation: 目的：通过选择性地随机化输入数据，提供数据存储设备和具有该数据存储设备的数据存储系统以增加随机性。 构成：控制器（20）决定第一输入数据的特性。 控制器基于所确定的第一输入数据的输入数据输出第一控制信号。 随机化器（10）响应于从控制器输出的第一控制信号选择性地使第一输入数据随机化。 纠错编码器（50）通过将第二输入数据编码到纠错码来产生第一输入数据。 解随机器（30）对从主机读取的命令进行读取的读取数据执行反向随机化。

公开(公告)号：KR1020090119117A

公开(公告)日：2009-11-19

申请号：KR1020080044964

申请日：2008-05-15

Applicant: 삼성전자주식회사

Inventor： 김용준 ,  김재홍 ,  공준진 ,  조경래

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/04

CPC classification number: G11C16/10 ,  G06F11/1072 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/3454 ,  G11C29/00 ,  G11C2211/5621 ,  G11C2211/5634

Abstract: PURPOSE: A memory device and a memory data error detection method for managing the error of data stored in the memory device are provided to achieve SSD(Solid State Drive/Disk) using non-volatile memory. CONSTITUTION: A memory device(900) includes a memory cell array, a reading unit, an error correction unit and a programming unit. The memory cell array includes memory cells. The reading unit reads data from memory cells. The forward error correction unit detects the erroneous bit of data. The forward error correction unit distinguishes the memory cell in which the bit detected among memory cells is stored.

Abstract translation: 目的：提供用于管理存储在存储设备中的数据的错误的存储器件和存储器数据错误检测方法，以使用非易失性存储器来实现SSD（固态硬盘/磁盘）。 构成：存储器件（900）包括存储单元阵列，读取单元，纠错单元和编程单元。 存储单元阵列包括存储单元。 读取单元从存储单元读取数据。 前向纠错单元检测数据的错误位。 前向纠错单元区分存储单元中检测到的位的存储单元。

公开(公告)号：KR1020090114972A

公开(公告)日：2009-11-04

申请号：KR1020080040877

申请日：2008-04-30

Applicant: 삼성전자주식회사

Inventor： 김용준 ,  김재홍 ,  조경래 ,  공준진 ,  이기준 ,  정하봉 ,  최근성

IPC: H04L27/26

CPC classification number: H03M13/451 ,  G06F11/1072

Abstract: PURPOSE: An encoding and decoding method of multi bit level data is provided to reduce a bit error in decoding failure by using a bit - symbol mapping table having a gray code or a bit - symbol mapping table. CONSTITUTION: In an encoding and decoding method of multi bit level data, a controller receives a transmission symbol from a transmitting end(S10). A controller detects a range of the error pattern based on a table including an error pattern of a transmission symbol and transmission symbol(S12). A controller encodes at least one of a plurality of multi-bit levels corresponding to the transmission symbol based on the range of the error pattern(S14). The controller detects at least one transmission candidate symbol corresponding to the receiving symbol. The controller detects at least one transmission candidate symbol corresponding to the receiving symbol based on a table including the transmission candidate symbol.

Abstract translation: 目的：提供多位电平数据的编码和解码方法，通过使用具有灰度码或位符号映射表的位符号映射表来减少解码失败中的位错误。 构成：在多位电平数据的编码和解码方法中，控制器从发送端接收发送符号（S10）。 控制器基于包括发送符号和发送符号的错误模式的表来检测错误模式的范围（S12）。 控制器基于错误模式的范围编码与发送符号相对应的多个多位电平中的至少一个（S14）。 控制器检测与接收符号对应的至少一个传输候选符号。 控制器基于包括传输候选符号的表来检测与接收符号相对应的至少一个传输候选符号。

公开(公告)号：KR1020080067799A

公开(公告)日：2008-07-22

申请号：KR1020070005158

申请日：2007-01-17

Applicant: 삼성전자주식회사

Inventor： 오치성 ,  김용준 ,  남경우 ,  김진국

IPC: G06F13/16 ,  G06F12/00 ,  G06F15/167 ,  G06F15/16

CPC classification number: G11C5/02 ,  G11C8/12

Abstract: A multi-path accessible semiconductor memory device having mail box regions and a method of controlling mail box access are provided to share a data input/output path, transmit a message through an additional message input/output line and minimize an increase in the number of message input/output lines to reduce a chip size. A multi-path accessible semiconductor memory device(100) includes at least one shared memory region(112) and mail box regions(260,270). The shared memory region is operatively connected to a plurality of independent ports(120,130), selectively accessed through a data access path formed between one of the ports, which is authorized, and the shared memory, and allocated to a memory cell array. The mail box regions are respectively provided for the ports for message communication among the ports and share a data input/output line which forms the data access path to be accessed corresponding to a specific address of the shared memory region.

Abstract translation: 提供具有邮箱区域的多路径可访问半导体存储器件和控制邮箱访问的方法以共享数据输入/输出路径，通过附加消息输入/输出线路发送消息并最小化数量的增加 消息输入/输出线以减少芯片尺寸。 多路径可访问半导体存储器件（100）包括至少一个共享存储区域（112）和邮箱区域（260,270）。 共享存储器区域可操作地连接到多个独立端口（120,130），其通过在被授权的一个端口和共享存储器之间形成并分配给存储器单元阵列的数据访问路径选择性地访问。 邮箱区域分别被提供用于端口之间的消息通信端口，并且共享一个数据输入/输出线路，该数据输入/输出线路形成对应于共享存储器区域的特定地址的要访问的数据访问路径。

公开(公告)号：KR1020080065827A

公开(公告)日：2008-07-15

申请号：KR1020070002958

申请日：2007-01-10

Applicant: 삼성전자주식회사

Inventor： 정우섭 ,  김용준 ,  이규찬

IPC: H01L21/66

CPC classification number: G11C29/56 ,  G01R31/318511 ,  G11C29/006 ,  G11C29/1201 ,  G11C29/48 ,  G11C2029/5602 ,  H01L2224/06156

Abstract: A semiconductor memory device and a method for testing the same are provided to secure contacting states of pads by increasing a pad size and a pad pitch in a wafer test process. A plurality of internal circuits are formed in a die. A plurality of first and second channel pads(20-1 to 20-(N+1),30-1 to 30-(N+1)) having a first pad size and a first pad pitch are alternately arranged in parallel to each other on a straight line of the die. The first and second channel pads alternately and selectively come in contact with test probes(150-1 to 150(N+1)) in order to receive a wafer test signal from the outside and to output signals of the internal circuits to the outside. A probe card is formed at an interval of the first or the second channel pads in order to test the first or the second channel pads.

Abstract translation: 提供一种半导体存储器件及其测试方法，用于通过在晶片测试过程中增加焊盘尺寸和焊盘间距来确保焊盘的接触状态。 在模具中形成多个内部电路。 具有第一焊盘尺寸和第一焊盘间距的多个第一和第二通道焊盘（20-1至20-（N + 1），30-1至30-（N + 1））与每个 另一个在模具的直线上。 第一和第二通道焊盘与测试探针（150-1至150（N + 1））交替选择性地接触，以便从外部接收晶片测试信号并将内部电路的信号输出到外部。 以第一或第二通道焊盘的间隔形成探针卡，以测试第一或第二通道焊盘。

公开(公告)号：KR100818725B1

公开(公告)日：2008-04-01

申请号：KR1020060082348

申请日：2006-08-29

Applicant: 삼성전자주식회사

Inventor： 김용준 ,  박종욱 ,  오치성

IPC: G11C11/401 ,  G11C11/4093

Abstract: 공유 뱅크를 가지는 멀티 포트 반도체 메모리 장치와 그 리프레시 방법이 개시된다. 상기 반도체 메모리 장치는 적어도 하나의 공유 뱅크를 구비하는 메모리 코어; 제1 포트 및 제2 포트; 및 상기 적어도 하나의 공유 뱅크를 선택적으로 상기 제1 또는 제2 포트를 통하여 대응되는 외부장치와 접속하도록 제어하는 권한 제어부를 구비하며, 상기 적어도 하나의 공유 뱅크는, 대응되는 외부장치로부터 출력된 제1명령에 기초하여 리프레시 동작을 수행하고, 상기 권한 제어부에 의하여 권한이 전환될 때마다 상기 리프레시 동작을 더 수행하여 리프레시 부족 현상을 방지할 수 있다.
공유 뱅크, 리프레시