公开(公告)号：US11158621B2

公开(公告)日：2021-10-26

申请号：US16880463

申请日：2020-05-21

Applicant: Apple Inc.

Inventor： Chonghua Zhong ,  Jun Zhai ,  Kunzhong Hu

IPC: H01L25/18 ,  H01L23/538 ,  H01L23/00

Abstract: Double side mounted package structures and memory modules incorporating such double side mounted package structures are described in which memory packages are mounted on both sides of a module substrate. A routing substrate is mounted to a bottom side of the module substrate to provide general purpose in/out routing and power routing, while signal routing from the logic die to double side mounted memory packages is provided in the module routing. In an embodiment, module substrate is a coreless module substrate and may be thinner than the routing substrate.

公开(公告)号：US11158607B2

公开(公告)日：2021-10-26

申请号：US16503806

申请日：2019-07-05

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Kwan-Yu Lai ,  Kunzhong Hu ,  Vidhya Ramachandran

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/768 ,  H01L21/78 ,  H01L21/66 ,  H01L23/48 ,  H01L23/60 ,  H01L23/00 ,  H01L25/00

Abstract: Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip includes a reconstituted chip-level back end of the line (BEOL) build-up structure to connect a die set embedded in an inorganic gap fill material.

公开(公告)号：US10985107B2

公开(公告)日：2021-04-20

申请号：US16583082

申请日：2019-09-25

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai

IPC: H01L23/48 ,  H01L21/44 ,  H01L23/538 ,  H01L23/488 ,  H01L23/00 ,  H01L25/18 ,  H01L21/66 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58 ,  H01L23/498

Abstract: Stitched die structures, and methods for interconnecting die are described. In an embodiment, a stitched die structure includes a semiconductor substrate that includes a first die area of a first die and a second die area of a second die separate from the first die area. A back-end-of-the-line (BEOL) build-up structure spans over the first die area and the second die area, and includes a first metallic seal directly over a first peripheral area of the first die area, a second metallic seal directly over a second peripheral area of the second die area, and a die-to-die routing extending through the first metallic seal and the second metallic seal to electrically connect the first die to the second die.

公开(公告)号：US20200381383A1

公开(公告)日：2020-12-03

申请号：US16423931

申请日：2019-05-28

Applicant: Apple Inc.

Inventor： Jun Chung Hsu ,  Chih-Ming Chung ,  Jun Zhai ,  Yifan Kao ,  Young Doo Jeon ,  Taegui Kim

IPC: H01L23/00

Abstract: Semiconductor packaging substrates and processing sequences are described. In an embodiment, a packaging substrate includes a build-up structure, and a patterned metal contact layer partially embedded within the build-up structure and protruding from the build-up structure. The patterned metal contact layer may include an array of surface mount (SMT) metal bumps in a chip mount area, a metal dam structure or combination thereof.

公开(公告)号：US10770433B1

公开(公告)日：2020-09-08

申请号：US16287635

申请日：2019-02-27

Applicant: Apple Inc.

Inventor： Chonghua Zhong ,  Jun Zhai ,  Kunzhong Hu

IPC: H01L25/065 ,  H01L23/24 ,  H01L25/18 ,  H01L23/538 ,  H01L25/00 ,  H01L23/00

Abstract: Package structure with folded die arrangements and methods of fabrication are described. In an embodiment, a package structure includes a first die and vertical interposer side-by-side. A second die is face down on an electrically connected with the vertical interposer, and a local interposer electrically connects the first die with the vertical interposer.

公开(公告)号：US20200279842A1

公开(公告)日：2020-09-03

申请号：US16880463

申请日：2020-05-21

Applicant: Apple Inc.

Inventor： Chonghua Zhong ,  Jun Zhai ,  Kunzhong Hu

IPC: H01L25/18 ,  H01L23/538

Abstract: Double side mounted package structures and memory modules incorporating such double side mounted package structures are described in which memory packages are mounted on both sides of a module substrate. A routing substrate is mounted to a bottom side of the module substrate to provide general purpose in/out routing and power routing, while signal routing from the logic die to double side mounted memory packages is provided in the module routing. In an embodiment, module substrate is a coreless module substrate and may be thinner than the routing substrate.

公开(公告)号：US20200273843A1

公开(公告)日：2020-08-27

申请号：US16287635

申请日：2019-02-27

Applicant: Apple Inc.

Inventor： Chonghua Zhong ,  Jun Zhai ,  Kunzhong Hu

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L23/538 ,  H01L23/24 ,  H01L23/00

Abstract: Package structure with folded die arrangements and methods of fabrication are described. In an embodiment, a package structure includes a first die and vertical interposer side-by-side. A second die is face down on an electrically connected with the vertical interposer, and a local interposer electrically connects the first die with the vertical interposer.

公开(公告)号：US20200176431A1

公开(公告)日：2020-06-04

申请号：US16204679

申请日：2018-11-29

Applicant: Apple Inc.

Inventor： Chonghua Zhong ,  Jun Zhai ,  Kunzhong Hu

IPC: H01L25/18 ,  H01L23/538

Abstract: Double side mounted package structures and memory modules incorporating such double side mounted package structures are described in which memory packages are mounted on both sides of a module substrate. A routing substrate is mounted to a bottom side of the module substrate to provide general purpose in/out routing and power routing, while signal routing from the logic die to double side mounted memory packages is provided in the module routing. In an embodiment, module substrate is a coreless module substrate and may be thinner than the routing substrate.

公开(公告)号：US20200176427A1

公开(公告)日：2020-06-04

申请号：US16205679

申请日：2018-11-30

Applicant: Apple Inc.

Inventor： Vidhya Ramachandran ,  Chonghua Zhong ,  Jun Zhai ,  Long Huang ,  Mengzhi Pang ,  Rohan U. Mandrekar

IPC: H01L25/16 ,  H01L21/66 ,  G01R31/02

Abstract: Integrated passive devices (IPDs), electronic packaging structures, and methods of testing IPDs are described. In an embodiment, an electronic package structure includes an IPD with an array of capacitor banks that are electrically separate in the IPD, and a package routing that includes an interconnect electrically connected to an IC and a plurality of the capacitor banks in parallel.

公开(公告)号：US10181455B2

公开(公告)日：2019-01-15

申请号：US15408263

申请日：2017-01-17

Applicant: Apple Inc.

Inventor： Jun Zhai ,  Chonghua Zhong ,  Kunzhong Hu ,  Se Young Yang

IPC: H01L21/48 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L25/18 ,  H01L21/56 ,  H01L25/00 ,  H01L21/768 ,  H01L21/683 ,  H01L21/78 ,  G11C14/00

Abstract: Package on package structures and methods of manufacture are described. In various embodiments, DRAM die are integrated into various locations within a package on package structure, including within a bottom logic die package, as a co-package with a top NAND die package, and as a hybrid package structure between a top NAND die package and a bottom logic die package.