公开(公告)号：FI72841C

公开(公告)日：1987-07-10

申请号：FI803868

申请日：1980-12-12

Applicant: RCA CORP

Inventor： STECKLER STEVEN ALAN ,  BALABAN ALVIN REUBEN

IPC: H04N5/06 ,  H04N3/16 ,  H04N3/185 ,  H04N5/12 ,  H04N3/18

公开(公告)号：PT84813A

公开(公告)日：1987-05-01

申请号：PT8481387

申请日：1987-04-30

Applicant: RCA CORP

Inventor： BALABAN ALVIN REBUEN ,  STECKLER STEVEN ALAN

IPC: H04N5/08 ,  H04N5/04

Abstract: A sync separator detects, in a corresponding part of the waveform of a video signal (100), the occurrence of the trailing edge of a corresponding sync pulse, in accordance with the rate of change of the video signal. Information obtained from the sync tip and the back porch portions of the corresponding sync pulse is used for generating a slice level signal (SL). A comparator (20) responsive to the slice level signal separates a sync signal (100a) from the video signal (100).

公开(公告)号：FR2474788B1

公开(公告)日：1986-10-31

申请号：FR8101625

申请日：1981-01-28

Applicant: RCA CORP

Inventor： BALABAN ALVIN REUBEN ,  STECKLER STEVEN ALAN

IPC: H03D13/00 ,  H04N5/12 ,  H03F3/45

Abstract: A differential amplifier is provided, including first and second emitter coupled transistors responsive to an input signal applied to one of their base electrodes, and a current source transistor having its collector-to-emitter path serially coupled between the coupled emitters of the first and second transistors and a point of reference potential. A current repeater circuit is coupled between the collector electrodes of the first and second transistors which comprises a current mirror for replicating the collector current of the first transistor. The current mirror includes third and fourth transistors having respective collector electrodes coupled to the collector electrodes of the first and second transistors, respectively, the base electrode of the third transistor being coupled to the base electrode of the fourth transistor, and a resistor for coupling the emitter electrode of at least one of the third and fourth transistors to a source of supply voltage. The collector current of the first transistor is substantially replicated by the collector current of the fourth transistor. A fifth transistor has its collector-to-emitter path serially coupled between the base electrodes of the third and fourth transistors and the resistor, and is biased to conduct a given magnitude of current when the third and fourth transistors are nonconductive and to lessen its conduction when the third and fourth transistors are conducting current.

公开(公告)号：FI71049C

公开(公告)日：1986-10-27

申请号：FI793025

申请日：1979-09-28

Applicant: RCA CORP

Inventor： BALABAN ALVIN REUBEN ,  STECKLER STEVEN ALAN

IPC: H04N5/12 ,  H04N5/04

公开(公告)号：AT22644T

公开(公告)日：1986-10-15

申请号：AT83304459

申请日：1983-08-02

Applicant: RCA CORP

Inventor： LEWIS HENRY GARTON JR ,  BALABAN ALVIN REUBEN ,  BOLGER THOMAS VINCENT ,  STECKLER STEVEN ALAN

IPC: H03H15/00 ,  H04N9/64 ,  H04N11/06

公开(公告)号：MY8500721A

公开(公告)日：1985-12-31

申请号：MY8500721

申请日：1985-12-30

Applicant: RCA CORP

Inventor： BALABAN ALVIN REUBEN ,  STECKLER STEVEN ALAN

IPC: H04N5/12 ,  H03L7/06

公开(公告)号：GB2154093A

公开(公告)日：1985-08-29

申请号：GB8402913

申请日：1984-02-03

Applicant: RCA CORP

Inventor： LEWIS HENRY GARTON ,  BOLGER THOMAS VINCENT ,  BALABAN ALVIN RUEBEN ,  STECKLER STEVEN ALAN

IPC: H04N9/78

Abstract: A system to separate components interleaved in frequency in the video input signal of a TV receiver, e.g. luminance and chrominance, samples the analogue signal at e.g. 4 fsc (i.e. 4xcolour subcarrier frequency). The signal is digitized (e.g. 8 bits) (10) and applied via a digital bandpass filter (12) and sub-sampler to a digital comb filter (20) working at a lower sampling rate (e.g. 2 fsc) to economise in storage locations. The comb filter output provides one component (chrominance) at a reduced sampling rate (2 fsc) and a second (luminance) at 4fsc may be obtained by interpolating (16) the first back to the original sampling rate (4fsc) and subtracting (18) from the original digitized signal.

公开(公告)号：DK147028C

公开(公告)日：1984-08-27

申请号：DK30675

申请日：1975-01-29

Applicant: RCA CORP

Inventor： STECKLER STEVEN ALAN ,  LIMBERG ALLEN LEROY

IPC: H04N5/06 ,  H04N5/04 ,  H04N5/08 ,  H04N5/12 ,  H04N5/213

Abstract: A dual mode deflection synchronizing system includes a resettable counter which generates noise-free internal synchronizing signals and signals representative of the interval during which external vertical synchronizing signals should be received provided the counter is properly synchronized. A sync signal verification detector is coupled to the source of external vertical sync signals and to a mode switch so that if the external signals arrive during this prediction interval as determined by the sync signal verification detector the system continues to operate in a synchronized mode on its internally generated synchronizing signals. If the external signals do not arrive during this prediction interval, the mode switch switches the system into a non-synchronized mode. A vertical sync signal detector which is also coupled to the source of external sync signals and to the mode switch begins to search for an external signal which has the time duration characteristic of an authentic external synchronizing signal. Until such a signal is received, the system continues to be synchronized by internal synchronizing signals generated by the resettable counter. When such a signal is received, the vertical sync signal detector resets the counter to correct its synchronization with the received external vertical synchronizing signal and toggles the mode switch to return the system to its synchronized mode of operation.

公开(公告)号：MX5833E

公开(公告)日：1984-07-31

申请号：MX10137182

申请日：1982-02-09

Applicant: RCA CORP

Inventor： FERNSLER RONALD EUGENE ,  STECKLER STEVEN ALAN ,  BALABAN ALVIN REUBEN

IPC: H04N3/00

公开(公告)号：MX150349A

公开(公告)日：1984-04-18

申请号：MX19130782

申请日：1982-02-09

Applicant: RCA CORP

Inventor： FERNSLER RONALD EUGENE ,  STECKLER STEVEN ALAN ,  BALABAN ALVIN REUBEN

IPC: H04N5/04 ,  H04N3/16 ,  H04N5/12 ,  H03K1/17

Abstract: A horizontal deflection turn-on circuit operates in the absence of trigger pulse normally derived by an AFPC loop. Under normal operation, the AFPC loop generates the trigger pulses based on a synchronized phase relationship with sampled flyback pulses. During receiver start-up, the flyback pulses are not present and no trigger pulses are generated. The turn on circuit provides auxiliary pulses which occur later in time than the normal occurrence of the trigger pulses. Means are provided for applying the auxiliary pulses to the horizontal deflection circuit only in the absence of normal trigger pulses.