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公开(公告)号：WO1982002637A1
公开(公告)日：1982-08-05
申请号：PCT/US1982000086
申请日：1982-01-25
Applicant: RCA CORP
Inventor： RCA CORP , STROLLE CHRISTOPHER HUGH , SMITH TERRANCE RAYMOND , LEWIS HENRY GARTON JR , ACAMPORA ALFONSE , REITMEIER GLENN ARTHUR
IPC: H04N05/02
CPC classification number: H04N9/78 , G06F1/0307 , G06F1/0353 , G06F1/0356 , G06F2101/04 , G06F2101/08 , G06F2101/10 , G06T3/00 , G09G5/395 , G11C7/00 , G11C8/04 , G11C8/16 , H04N9/646
Abstract: A digital memory (10) which contains digital data words representative of a desired symmetrical transfer characteristic of a digital signal processor. Digital signals which are to be processed are applied to the address inputs of the memory (10), producing output signals in conformance with the desired transfer characteristic. Advantage is taken of the symmetrical nature of the response characteristic to minimize the size of the memory. Data words corresponding to only a portion of the full dynamic range of the digital signal processor are stored in the memory (10), and memory locations are addressed and read out in accordance with the value of a polarity-determining bit of the input digital signal, with the output signals being translated over the required full dynamic range in accordance with the value of the polarity-determining bit. In a preferred embodiment of the invention, the memory (10) is a random access memory, with stored data values being altered in response to a user control to change the transfer characteristic of the processor.
Abstract translation: 数字存储器（10），其包含表示数字信号处理器的期望对称传送特性的数字数据字。 要处理的数字信号被施加到存储器（10）的地址输入端，产生符合期望传输特性的输出信号。 利用响应特性的对称性优点来最小化存储器的大小。 仅对应于数字信号处理器的全部动态范围的一部分的数据字被存储在存储器（10）中，并且根据输入数字信号的极性确定位的值来寻址和读出存储单元 ，其中输出信号根据极性确定位的值在所需的全动态范围内转换。 在本发明的优选实施例中，存储器（10）是随机存取存储器，响应于用户控制改变存储的数据值，改变处理器的传送特性。
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公开(公告)号：EP0070311A4
公开(公告)日：1985-06-06
申请号：EP82900743
申请日：1982-01-25
Applicant: RCA CORP
Inventor： STROLLE CHRISTOPHER HUGH , SMITH TERRANCE RAYMOND , LEWIS HENRY GARTON JR , ACAMPORA ALFONSE , REITMEIER GLENN ARTHUR
IPC: G06F1/03 , G06F1/035 , G06T3/00 , G09G5/395 , G11C7/00 , G11C8/04 , G11C8/16 , H04N9/64 , H04N9/78 , H04N5/02
CPC classification number: H04N9/78 , G06F1/0307 , G06F1/0353 , G06F1/0356 , G06F2101/04 , G06F2101/08 , G06F2101/10 , G06T3/00 , G09G5/395 , G11C7/00 , G11C8/04 , G11C8/16 , H04N9/646
Abstract: A digital memory (10) which contains digital data words representative of a desired symmetrical transfer characteristic of a digital signal processor. Digital signals which are to be processed are applied to the address inputs of the memory (10), producing output signals in conformance with the desired transfer characteristic. Advantage is taken of the symmetrical nature of the response characteristic to minimize the size of the memory. Data words corresponding to only a portion of the full dynamic range of the digital signal processor are stored in the memory (10), and memory locations are addressed and read out in accordance with the value of a polarity-determining bit of the input digital signal, with the output signals being translated over the required full dynamic range in accordance with the value of the polarity-determining bit. In a preferred embodiment of the invention, the memory (10) is a random access memory, with stored data values being altered in response to a user control to change the transfer characteristic of the processor.
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公开(公告)号：FR2547475B1
公开(公告)日：1989-10-13
申请号：FR8408877
申请日：1984-06-06
Applicant: RCA CORP
Inventor： LEWIS HENRY GARTON JR , STILLER THOMAS MICHAEL
Abstract: In a digital television receiver, a signal processing stage generates color mixture digital signals representing color picture information as components in a first color mixture coordinate system such as the I-Q system. The I and Q digital signals are applied to a read only memory look-up table in which memory locations are stored the logarithmic values of the signals in order to convert the signals into digital words represented in logarithmic form. A microprocessor or other digital circuit generates or retrieves digital coefficients in logarithmic form that enable the I and Q digital signals to be transformed into second color mixture digital signals representing the color picture information as components in a second color mixture coordinate system such as the R-Y, B-Y, color difference coordinate system. The I and Q digital signals in logarithmic form are applied to a first input of an adder. A digital store stores the coefficients, and a multiplexer coupled to the digital store supplies to a second input of the adder a sequence of coefficients in the same order corresponding to the sequence of I and Q digital signals being applied to the first input of the adder. At the output of the adder there is developed a plurality of products in logarithmic form that correspond to the values of the I and Q constituents of the R-Y, B-Y digital signals. The plurality of products are applied to an antilog read only memory look-up table in which memory locations are stored the inverse logarithmic values of the I and Q constituents. A second adder receives the output of the antilog ROM, now in straight arithmetic form, to obtain the R-Y, B-Y or G-Y color difference signals.
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公开(公告)号：FR2536940B1
公开(公告)日：1989-01-20
申请号：FR8318862
申请日：1983-11-25
Applicant: RCA CORP
Inventor： LEWIS HENRY GARTON JR
Abstract: In a color television receiver with a digital signal processing system, a chroma processor operates on digital samples containing color picture information to develop first and second binary coded digital signals containing two color mixture signal information such as I color mixture information and Q color mixture information. A luminance processor operates on the digital samples to develop a third digital signal containing Y or luminance information. R, G and B digital signals are related to the developed I, Q and Y digital signals by a set of coefficient multipliers. To obtain the R, G and B digital signals, the I, Q and Y digital signals are applied to a digital decoder that includes a ROM look-up table multiplier for multiplying each of the I, Q and Y signals by the appropriate coefficient multiplier. The products thus generated are summed in an adder to obtain each of the R, G and B signals. A digital-to-analog converter develops analog R, G and B voltages for driving the cathode electrodes of the television receiver color picture tube.
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公开(公告)号：FR2588143A1
公开(公告)日：1987-04-03
申请号：FR8613532
申请日：1986-09-29
Applicant: RCA CORP
Inventor： LEWIS HENRY GARTON JR
Abstract: A recursive filter for noise reducing composite video signal separately processes the luminance and chrominance components of the composite signal but requires only a single frame of storage. Input composite video signal is separated into luminance and chrominance component signals. The component signals are coupled to separate signal recursion scaling/combining circuits. The outputs from the recursion circuits are summed in an adder to produce noise-reduced composite video signal which is applied to a frame delay element. The output of the delay element is applied to a chroma/luma separator which separates the luminance and chrominance components and applies them to the respective recursion circuits.
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Patent Agency Ranking
公开(公告)号：FR2562366A1
公开(公告)日：1985-10-04
申请号：FR8504710
申请日：1985-03-28
Applicant: RCA CORP
Inventor： LEWIS HENRY GARTON JR
IPC: H04N9/68
Abstract: Gain control of signals processed in a digital TV receiver is split between serially connected coarse and fine gain blocks. The coarse gain block consists of bit shifters to shift the sample bits to greater or lesser significant bit positions which provides a 6 dB gain change for each bit position change. Fine gain control is performed in the digital-to-analog converters which ultimately produce the analog signals for driving the display tube. The digital-to-analog converters are selectively reset each sample period with reset pulses that are developed by a fine gain control. The output signal from the digital to analog converter is an amplitude and pulse width modulated signal. The average amplitude of the signal over a sample period is determined by the pulse width and is thus a function of the fine gain control.
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公开(公告)号：FR2549331A1
公开(公告)日：1985-01-18
申请号：FR8409915
申请日：1984-06-22
Applicant: RCA CORP
Inventor： LEWIS HENRY GARTON JR
IPC: H04N9/77
Abstract: Digital TV receivers which digitally process chroma and luma signals in different channels and convert the digital signals to analog form before matrixing will include low pass analog filters after the DAC's to remove clock switching components. The luma and chroma analog filters will impose differing group delay on their respective signals. This creates a differential phase error between the analog signals which is corrected by predictively delaying the signal which leads in phase in the DAC. This is accomplished by using clocked digital-to-analog converters forced to operate synchronously with the data stream and appropriately delaying the clock signal applied to one of the DAC's relative to the other.
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公开(公告)号：FR2512304A1
公开(公告)日：1983-03-04
申请号：FR8214803
申请日：1982-08-30
Applicant: RCA CORP
Inventor： LEWIS HENRY GARTON JR
Abstract: A digital filter arrangement is provided which both demodulates and filters the color mixture signals in a television receiver. Samples of a digital chrominance signal are clocked into first and second registers such that the first register is loaded with samples of a first color mixture signal and the second register contains samples of a second color mixture signal. Output taps are connected between various ones of the stages of the first and second registers and weighting function circuits. The weighting function circuits associated with each register are in turn coupled to respective ladder networks of adders, which combine the weighted signals samples so as to exhibit, at an output stage adder, a lowpass response characteristic which is appropriate for the respective color mixture signal. The two digital registers are aligned in time in accordance with their respective peak impulse response characteristic to product filtered color mixture signals in a proper timed relationship.
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公开(公告)号：FR2599574B1
公开(公告)日：1990-08-31
申请号：FR8707518
申请日：1987-05-27
Applicant: RCA CORP
Inventor： CAMPBELL EDWARD RICHARD III , LEWIS HENRY GARTON JR
Abstract: In a television receiver including an automatic deghosting system 24, Fig. 1 (634, Fig. 6) means 18, 22 are provided for synchronously demodulating IF television signals to generate baseband signals representing the in phase (I) and quadrature phase (Q) modulation components of the IF signals. A carrier signal extractor circuit 14 extracts the received carrier signal from the radio frequency television signal. A phase locked loop 16 coupled to the carrier signal extracting circuit generates a phase difference signal representing the difference in phase between the oscillatory and the extracted carrier signals. A demodulation phase error detector 26, (630) coupled to the synchronous demodulation means generates a phase control signal proportional to the difference in phase between the direct carrier signal as broadcast and the received carrier signal which may include ghosts. A phase correction circuit 312, 316, 318, Fig. 3 or a ROM (632, Fig. 6) responds to the phase control signal and modifies the phase difference signal (or the first baseband signal) to generate a modified first baseband signal with substantially reduced crosstalk distortion components.
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公开(公告)号：IT1214487B
公开(公告)日：1990-01-18
申请号：IT2013585
申请日：1985-03-28
Applicant: RCA CORP
Inventor： LEWIS HENRY GARTON JR
Abstract: Gain control of signals processed in a digital TV receiver is split between serially connected coarse and fine gain blocks. The coarse gain block consists of bit shifters to shift the sample bits to greater or lesser significant bit positions which provides a 6 dB gain change for each bit position change. Fine gain control is performed in the digital-to-analog converters which ultimately produce the analog signals for driving the display tube. The digital-to-analog converters are selectively reset each sample period with reset pulses that are developed by a fine gain control. The output signal from the digital to analog converter is an amplitude and pulse width modulated signal. The average amplitude of the signal over a sample period is determined by the pulse width and is thus a function of the fine gain control.
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