公开(公告)号：JPS61196579A

公开(公告)日：1986-08-30

申请号：JP3679485

申请日：1985-02-26

Applicant: SONY CORP

Inventor： KAMATA MIKIO

IPC: H01L29/812 ,  H01L21/338 ,  H01L29/778 ,  H01L29/80

Abstract: PURPOSE:To position source and gate regions and a gate region to be interposed therebetween in a predetermined positional relation (self alignment) and to set an offset precisely and uniformly, by utilizing first and second mask layers in combination. CONSTITUTION:A semiconductor substrate S is provided thereon with a first mask layer 3 having a predetermined width W corresponding to the length of a gate. A second mask layer 4 is further provided on the layer 3. The first mask layer 3 has, in its sections adjacent to the opposing side faces 3a1 and 3a2, a thickness d1 sufficiently larger than a thickness d2 in the other sections, and a width Ws in these thicker sections 4a is determined corresponding to an interval (offset) between gate and source regions and between gate and drain regions. The interval between the source and drain regions 5 and 6 is determined corresponding to the sum of the width Ws of the thicker section 4a and the width W. The second mask layer 4 is etched to expose the first mask layer 3, and a window 4W is opened in the second mask layer 4. A gate region 8 is provided while forming a gate junction J. The offset is set to be a predetermined narrow interval Wo.

公开(公告)号：JPS61147578A

公开(公告)日：1986-07-05

申请号：JP27035084

申请日：1984-12-21

Applicant: SONY CORP

Inventor： KATO YOJI ,  WATANABE SEIICHI ,  KAMATA MIKIO

IPC: H01L29/812 ,  H01L21/338 ,  H01L29/43 ,  H01L29/778

Abstract: PURPOSE:To obtain a heterojunction FET with 0 volt of threshould voltage by a method wherein an undoped AlGaAs layer, whose forbidden band gas is smaller than those of the gate electrode being constituted of a polycrystalline silicon film and the undoped GaAs layer, is provided between the gate electrode and the undoped GaAs layer. CONSTITUTION:Firstly, an undoped GaAs layer 2 and an undoped AlGaAs layer 13 are formed in order on a semiconductor GaAs substrate 1. Then, a polycrystalline silicon film 15 is formed on the layer 13. The film 15 is removed by performing an etching using a photo resist 16 as a mask and an electrode 5 is formed. An Au-Ge film 17 is evaporated on the whole surface to form a source electrode 6 and a drain electrode 7. After that the Au-Ge film 17 and the photo resist 16, which are on the electrode 5, are removed. The Au-Ge film 17 constituting each electrode 6 and 7 and the layers 13 and 2 are all formed into an alloy to form a source region 8 and a drain region 9. By this way, the heterojunction FET is obtained.

公开(公告)号：JPS61120477A

公开(公告)日：1986-06-07

申请号：JP24173684

申请日：1984-11-16

Applicant: Sony Corp

Inventor： TOGASHI HIROSHI ,  FUJII YOSHIAKI ,  KAMATA MIKIO ,  TAKAKUWA HIDEMI ,  FUTAKI MAKOTO

IPC: H01L21/338 ,  H01L29/08 ,  H01L29/417 ,  H01L29/812

CPC classification number: H01L29/0891 ,  H01L29/812

Abstract: PURPOSE:To obtain a device with good reproducibility, by depositing a Schottky metal layer on a semi-insulating semiconductor substrate, providing a mask, which has opening parts corresponding to source and drain regions, implanting ions, thereafter removing the exposed metal layer by annealing, and making the metal layer to remain beneath the mask as an electrode. CONSTITUTION:Si ions are implanted in the surface layer part of a semi- insulating GaAs substrate 21. Thereafter, a shallow N type active layer 22 is formed by annealing. A Schottky metal layer 23 comprising WSi is deposited thereon. The layer is coated by an SiO2 layer 24. Then, opening parts 26 and 25 are provided in correspondence with source and drain regions to be formed. Si ions are implanted through the layer 23. An N type source region 27 and a drain region 28, which are deeper than the layer 22, are formed in the layer 22 by annealing. Then the unnecessary layer 24 is removed. The layer 23 at both ends, which is exposed by said removal of the layer 24, is removed. The layer 23, which is exposed only between the regions 27 and 28, is made to remain as a Schottky electrode 29.

Abstract translation: 目的：为了获得具有良好重现性的器件，通过在半绝缘半导体衬底上沉积肖特基金属层，提供具有对应于源区和漏区的开口部分的掩模，注入离子，然后通过退火除去暴露的金属层 ，并且使金属层作为电极保持在掩模下方。 构成：将Si离子注入到半绝缘GaAs衬底21的表层部分中。此后，通过退火形成浅N型有源层22。 包含WSi的肖特金属层23沉积在其上。 该层被SiO 2层24涂覆。然后，与要形成的源区和漏区相对应地设置开口部26和25。 通过层23注入Si +离子。通过退火在层22中形成比层22深的N +型源极区27和漏极区28。 然后去除不需要的层24。 去除通过所述去除层24暴露的两端的层23。 使仅暴露在区域27和28之间的层23被保持为肖特基电极29。

公开(公告)号：JPS61100976A

公开(公告)日：1986-05-19

申请号：JP22239284

申请日：1984-10-23

Applicant: Sony Corp

Inventor： KAMATA MIKIO

IPC: H01L29/812 ,  H01L21/338 ,  H01L29/201 ,  H01L29/43 ,  H01L29/778

CPC classification number: H01L29/201 ,  H01L29/432 ,  H01L29/778

Abstract: PURPOSE:To increase and stabilize electronic mobility by forming a second semiconductor layer by three element group or more in low impurity- concentration and by superlattice structure in a field-effect transistor having double hetero-structure. CONSTITUTION:An intrinsic GaAs single crystal substrate as a first semiconduc tor layer 1 is formed, and an epitaxial layer (AlAs)m(GaAs)n (m and n are actual integers) second semiconductor layer 2 having superlattice structure shaped by repeatedly laminating each monatomic or plural atomic layers of AlAs and GaAs is formed onto the layer 1 through MOCVD. An n type im purity, such as Si, S, Se, etc. is doped continuously onto the second semiconduc tor layer 2, and the GaAs layer is epitaxy-grown, thus shaping a third semicon ductor layer 3. Third semiconductor layer 3 itself is used as a gate electrode, or a gate electrode is applied onto the third semiconductor layer 3 in an ohmic manner. A source and drain each region 4 and 5 into which an impurity such as the n type one is doped selectively in high concentration is formed to the first semiconductor layer 1 on both sides of the gate section while holding the gate section.

Abstract translation: 目的：通过在具有双异质结构的场效应晶体管中以低杂质浓度和超晶格结构形成第三半导体层，增加并稳定电子迁移率。 构成：形成作为第一半导体层1的本征GaAs单晶衬底，并且外延层（AlAs）m（GaAs）n（m和n是实际整数）具有超晶格结构的第二半导体层2， 通过MOCVD在层1上形成单原子或多个原子层的AlAs和GaAs。 将n型im纯度，例如Si，S，Se等连续地掺杂到第二半导体层2上，并且GaAs层被外延生长，从而成形第三半导体层3。第三半导体层3本身 用作栅电极，或者以欧姆方式将栅电极施加到第三半导体层3上。 在保持栅极部分的同时，在栅极部分的两侧形成第一半导体层1和漏极，其中诸如n型杂质的多个区域4和5以高浓度选择性地掺入其中。

公开(公告)号：JPS6149476A

公开(公告)日：1986-03-11

申请号：JP17118384

申请日：1984-08-17

Applicant: Sony Corp

Inventor： KAMATA MIKIO

IPC: H01L29/812 ,  H01L21/338 ,  H01L29/778

CPC classification number: H01L29/7782

Abstract: PURPOSE:To inhibit a short-channel effect by forming a barrier to carriers passing through a channel by a hetero-junction oppositely shaped to the channel. CONSTITUTION:An additional semiconductor layer 12, a first semiconductor layer 14 forming a channel 13 by a two demensional electron gas layer, and a second semiconductor layer 15, an energy gap thereof is larger than the layer 14 and which shapes a hetero-junction 16 between the layer 14 and itself, are grown on a substrate 11 in succession, thus constituting a semiconductor base body 18. A Schottky gate metal 17 shaping a Schottky junction 16 on the interface between the layer 15 and itself is applied onto the layer 15. Source and drain electrodes 9 and 20 are formed on both sides of the metal 17. According to the constitution, barriers by the hetero-junction are formed while facing the channel, thus confining carriers into the channel, then inhibiting a direct proceeding toward a drain from a source of carriers by a short channel effect.

Abstract translation: 目的：通过与通道相反的异质结通道通过通道的载流子形成屏障，来抑制短沟道效应。 构成：附加半导体层12，通过二维电子气层形成沟道13的第一半导体层14和第二半导体层15的能隙大于层14，并且形成异质结16 层14与本身之间，依次生长在基板11上，从而构成半导体基体18.在层15上施加将层15与界面之间的肖特基结16整形的肖特基栅极金属17。 源极和漏极9和20形成在金属17的两侧。根据该结构，在面向通道的同时形成异质结的障碍物，从而将载流子限制在通道中，然后阻止直接进入漏极 从一个来源的运营商通过一个短的渠道效应。

公开(公告)号：JPS6135561A

公开(公告)日：1986-02-20

申请号：JP15815084

申请日：1984-07-28

Applicant: Sony Corp

Inventor： KAMATA MIKIO

IPC: H01L29/812 ,  H01L21/338 ,  H01L21/339 ,  H01L29/76 ,  H01L29/762 ,  H01L29/765 ,  H01L29/768 ,  H01L29/772 ,  H01L29/778 ,  H01L29/78

CPC classification number: H01L29/765 ,  H01L29/76825 ,  H01L29/76833

Abstract: PURPOSE:To reduce a dark current by forming a semiconductor layer portion reducing a divergent current running into a channel from the first semiconductor layer side in a position at a necessary distance from a heterojunction on the first semiconductor layer. CONSTITUTION:In the first semiconductor layer 1 in which a channel portion 35 is formed or in a semiconductor substrate, in a position at a necessary distance d from the heterojunction JH2 between the second and the first semiconductor layers 2 and 1, the semiconductor layer porton 36, reducing by controlling a generation of an electron-hall pair to oppose to the channel 35 or by controlling or blocking a divergent current to the channel portion 35 by this generation, is formed along the surface of a substrate 31. Thus, the device can avoid effectively the generation of a dark current and form a CCD with a high S/N in spite of forming the CCD by the two-dimensional gas channel.

Abstract translation: 目的：通过形成半导体层部分来减小暗电流，从而在与第一半导体层上的异质结必要距离的位置减小从第一半导体层侧流入沟道的发散电流。 构成：在形成沟道部分35的第一半导体层1或半导体衬底中，在与第二和第一半导体层2和1之间的异质结JH2必需距离d的位置处，半导体层端口 如图36所示，沿着基板31的表面形成通过控制与沟道35相对的电子霍夫对的产生或者通过这样生成来控制或阻挡向通道部35的发散电流的减少。因此， 尽管通过二维气体通道形成CCD，仍然可以有效地避免产生暗电流并形成具有高S / N的CCD。

公开(公告)号：JPS60263475A

公开(公告)日：1985-12-26

申请号：JP12024784

申请日：1984-06-12

Applicant: SONY CORP

Inventor： KAMATA MIKIO

IPC: H01L29/812 ,  H01L21/338 ,  H01L21/8222 ,  H01L27/082 ,  H01L29/205 ,  H01L29/778

Abstract: PURPOSE:To avoid performance degradation and instability attributable to doping by a method wherein a normal-ion FET is easily obtained by using 2DEG to build a channel and adopting a double heterojunction-type construction wherein the two barriers are different from each other in respect of height. CONSTITUTION:A first heterojunction JH1 is formed between a third and second semiconductor layers 3 and 2, and a second heterojunction JH2 is formed between the second and first semiconductors 2 and 1. As for the heights DELTAEC1 and DELTAEC2 of the barriers belonging respectively to the heterojunctions JH1 and JH2, their relationship is expressed by an inequality DELTAEC1