公开(公告)号：EP1912121A1

公开(公告)日：2008-04-16

申请号：EP06425632.4

申请日：2006-09-13

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Micheloni, Rino ,  Ravasio, Roberto ,  Marelli, Alessia

IPC: G06F11/10 ,  G06F11/20

CPC classification number: G11C29/82 ,  G06F11/1068 ,  G11C29/24 ,  G11C2029/0411

Abstract: Basic redundancy information is non volatily stored in a reserved area (that is an area of the array that is not addressable by the user of the device) of the addressable area of the array and is copied on volatile storage supports at every power-on of the memory device.
The unpredictable though statistically inevitable presence of fail array elements also in such a reserved area of the memory array that would corrupt the basic redundancy information as established during the test-on wafer (EWS) phase of the fabrication process and thus increasing the number of rejects, lowering the yield of the fabrication process, is effectively overcome by writing the basic redundancy data in the reserved area of the array with an ECC technique, using a certain error correction code that may be chosen among so-called majority codes 3, 5, 7, 15 and the like or Hamming code for 1, 2, 3 or more errors, in function of the fail probability of a memory cell as determined by the testing on wafer of the devices during fabrication (fail probability of the specific fabrication process used).
A significant area saving is achieved compared to the use of fuse arrays and other known approaches.

Abstract translation: 基本冗余信息不会被浪费地存储在阵列的可寻址区域的保留区域（即阵列的不能由设备的用户可寻址的区域）中，并且在每次上电时复制到易失性存储器支持 存储设备。 在存储器阵列的这种保留区域中，不可预测的存在故障阵列元件的不可避免的存在将损坏在制造过程的测试晶片（EWS）阶段期间建立的基本冗余信息，从而增加了拒绝数量 通过使用可以在所谓的多数代码3,5中选择的某个纠错码，使用ECC技术将基本冗余数据写入阵列的保留区域中，有效地克服了降低制造处理的产量， 7,15等等或Hamming代码用于1,2,3或更多的错误，其功能是通过在制造期间在器件的晶片上的测试（使用特定制造过程的故障概率）确定的存储器单元的故障概率 ）。 与使用保险丝阵列和其他已知方法相比，实现了显着的面积节省。

公开(公告)号：EP1909290A1

公开(公告)日：2008-04-09

申请号：EP06119452.8

申请日：2006-08-24

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Micheloni, Rino ,  Crippa, Luca ,  Ravasio, Roberto ,  Pio, Federico

IPC: G11C16/34

CPC classification number: G11C16/344

Abstract: A method for operating a flash memory device ( 100 ) is proposed. The memory device includes a matrix of memory cells ( 110 ) each one having a programmable threshold voltage (V T ) defining a value stored in the memory cell. The method includes the steps of crasing a block ( 115 ) of memory cells, and compacting the threshold voltages of the memory cells of the block within a predefined compacting range, wherein the step of compacting includes: selecting at least one first memory cell (110 0e ) of the block for writing a target value; restoring the threshold voltage of a subset (110 0e ; 110 1o ) of the memory cells of the block to the compacting range, the subset consisting of the at least one first memory cell (110 0e ) and/or at least one second memory cell of the block (110 1o ) being adjacent to the at least one first memory cell; and at least partially writing the target value into the at least one first memory cell.

Abstract translation: 一种用于操作闪存器件（100）的方法，提出了 所述存储器装置包含存储单元的矩阵（110）每一个具有 - 定义存储在存储单元中的值的可编程阈值电压（V T）。 该方法包括crasing存储器单元的块（115），以及预定义的压实范围内压实块的存储器单元的阈值电压，worin压实的步骤的步骤包括：选择至少一个第一存储单元（110 0E）用于写入目标值的块的; 的子集的阈值电压（110 0E; 110 1O）恢复该块的存储器单元内的压实范围，所述子集由......组成所述至少一个第一存储单元（110奥斯特）和/或至少一个第二存储单元 块（110 1O）邻近所述至少一个第一存储单元的; 并至少部分地写入目标值到所述至少一个第一存储单元。

公开(公告)号：EP1901309A1

公开(公告)日：2008-03-19

申请号：EP06425631.6

申请日：2006-09-13

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Crippa, Luca ,  Ravasio, Roberto ,  Micheloni, Rino

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/32 ,  G11C29/00

CPC classification number: G11C29/02 ,  G11C16/04 ,  G11C29/023 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50012 ,  G11C2029/1204

Abstract: The evaluation time (Teval) of the programmed or erased state of a cell of the NAND memory array is set for the individual memory device in a way that at least partially compensates the generally large spread of parasitic capacitance values of the array bitlines in the mass production fabrication process of these devices.

Abstract translation: NAND存储器阵列的单元的编程或擦除状态的评估时间（Teval）以单个存储器件的方式被设置，该方式至少部分补偿了质量中阵列位线的寄生电容值的普遍大的扩展 这些设备的生产制造过程。

公开(公告)号：EP1892720A1

公开(公告)日：2008-02-27

申请号：EP06119479.1

申请日：2006-08-24

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Micheloni, Rino ,  Ravasio, Roberto

IPC: G11C11/56 ,  G11C16/10

CPC classification number: G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5641

Abstract: A solid-state mass storage device (105, 100; 400, 415, 420) is provided. The solid-state mass storage device defines a storage area (100; 415) adapted to store data; the storage area is adapted to be exploited for storing data with a first storage density at a first data transfer speed. The storage area comprises at least a first storage area portion (120) and a second storage area portion (130). The solid-state mass storage device further includes accessing means (105; 420, 440) adapted to exploit the first storage area portion for storing data with a second storage density at a second data transfer speed, and adapted to exploit the second storage area portion for storing data with a third storage density and a third data transfer speed. The second storage density is lower than the third storage density, which is in turn lower than or equal to the first storage density; the second data transfer speed is higher than the third data transfer speed, which is in turn higher than or equal to the first data transfer speed.

Abstract translation: 一种固态大容量存储设备（105，100; 400，415，420）被提供。 固态大容量存储设备定义的存储区域（100; 415）angepasst存储数据; 存储区域是angepasst被利用用于与在第一数据传输速度的第一存储密度存储数据。 存储区域至少包括部分第一存储区（120）和在部分的第二存储区域（130）。 固态大容量存储设备进一步包括存取装置（105; 420，440）angepasst利用在部分第一存储区域用于在第二数据传输速度与第二存储密度存储数据，并angepasst利用在部分第二存储区域 用于与第三存储密度和第三数据传送速度存储数据。 第二存储密度低于第三存储密度下，所有其又低于或等于第一存储密度; 第二数据传送速度高于第三数据传送速度时，所有这一切都高于或等于第一数据传送速度反过来。

公开(公告)号：EP1883076A1

公开(公告)日：2008-01-30

申请号：EP06425536.7

申请日：2006-07-28

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Crippa, Luca ,  Ravasio, Roberto ,  Micheloni, Rino

IPC: G11C16/10 ,  G11C11/56

CPC classification number: G11C16/10 ,  G11C7/18 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3427

Abstract: The capacitive coupling between two adjacent bitlines of a NAND memory device is relevant and this may be exploited for boosting the voltage of bitlines that are not to be programmed in order to inhibit program operations on them.
According to the disclosed method, first the even (odd) bitlines that include cells not to be programmed (BLE ,...,BLE ) are biased with a first voltage for inhibiting them from being programmed, typically the supply voltage (VDD), while the even (odd) bitlines that include cells to be programmed are grounded. Successively, the adjacent odd (even) bitlines (BLO ,...,BLO ) are biased at the supply voltage (VDD) or at an auxiliary voltage, for boosting the bias voltage of the even (odd) bitlines above the supply voltage.
With this expedient, the bias voltage of the even (odd) bitlines that include cells not to be programmed is boosted because of the relevant parasitic coupling capacitances between adjacent bitlines. Therefore, no dedicated charge pump generator is needed.

Abstract translation: NAND存储器件的两个相邻位线之间的电容耦合是相关的，并且这可以用于提升不被编程的位线的电压，以便阻止对它们的编程操作。 根据所公开的方法，首先，包含不被编程的单元（BLE <1>，...，BLE ）的偶数（奇数）位线被用于阻止它们被编程的第一电压偏置，通常 电源电压（VDD），而包括要编程的单元的偶数（奇数）位线接地。 接着，相邻的奇数（偶数）位线（BLO <0>，...，BLO ）偏置在电源电压（VDD）或辅助电压，用于升压偶数（奇数） 位于电源电压以上。 通过这种方式，由于相邻位线之间的相关寄生耦合电容，包括不编程单元的偶数（奇数）位线的偏置电压会升高。 因此，不需要专用的电荷泵发电机。

公开(公告)号：EP1870901A1

公开(公告)日：2007-12-26

申请号：EP06115809.3

申请日：2006-06-21

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Crippa, Luca ,  Micheloni, Rino

IPC: G11C11/56 ,  G11C7/10 ,  G11C16/24

CPC classification number: G11C7/1021 ,  G11C7/1039 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3459 ,  G11C2211/5621

Abstract: A page buffer (130) comprised in an electrically programmable memory device (100) is provided. The memory device includes also a plurality of memory cells (110), a plurality of distinct programming states defined for each memory cell, corresponding to a number N>=2 of data bits storable in each memory cell, and at least one read/program unit (205) having a coupling line (SO) operatively associable with selected memory cells. The read/program unit is adapted to at least temporarily store data bits read from or to be written into selected memory cells and comprises programming state change enabling means (230-1,230-2,252,254,256,258,272,274,276,278) for selectively enabling a change in programming state of a selected memory cell by causing the coupling line to take one among a program enabling potential and a program inhibition potential. The programming state change enabling means comprises reading means (256,258,260,230-2), receiving means (252,254,230-1), and combining means (272,274) activatable during a combining phase. The combining means includes a coupling electrical path between the reading means and the receiving means, said coupling electrical line being kept isolated from the coupling electrical path during said combining phase.

Abstract translation: 提供包括在电可编程存储器件（100）中的页缓冲器（130）。 存储器件还包括多个存储器单元（110），对于每个存储器单元定义的多个不同的编程状态，对应于可存储在每个存储单元中的数据位数N> = 2，以及至少一个读/ 单元（205）具有与所选择的存储器单元可操作地相关联的耦合线（SO）。 读/写单元适于至少临时存储从或将被写入所选择的存储单元中的数据位，并且包括编程状态改变使能装置（230-1,230-2,252,254,256,258,272,274,276,278），用于选择性地启用所选存储器的编程状态的改变 通过使耦合线在程序使能电位和程序禁止电位之间采取一个单元。 编程状态改变使能装置包括读取装置（256,258,260,230-2），接收装置（252,254,230-1）以及在组合阶段可激活的组合装置（272,274）。 组合装置包括在读取装置和接收装置之间的耦合电路，所述耦合电线在所述组合阶段期间与耦合电路保持隔离。

公开(公告)号：EP1837880A1

公开(公告)日：2007-09-26

申请号：EP06113480.5

申请日：2006-05-04

Applicant: STMicroelectronics S.r.l.

Inventor： Campardo, Giovanni ,  Micheloni, Rino

IPC: G11C8/08 ,  G11C16/12

CPC classification number: A61K31/737 ,  G11C5/145 ,  G11C8/08 ,  G11C16/12 ,  H01L27/0266 ,  H03K17/005 ,  H03K17/102 ,  H03K17/693 ,  Y10T307/675

Abstract: A row selector for a semiconductor memory including a plurality of memory cells coupled to a corresponding plurality of word lines, the row selector comprising, for each word line: a first biasing circuit path (230;215;260) adapted to bias the corresponding word line to a programming voltage when said corresponding word line is selected for selectively performing a program operation on at least one memory cell coupled to the corresponding word line, the first biasing circuit path comprising programming voltage provisioning means (215) adapted to provide the programming voltage; a second biasing circuit path (235) which is adapted to receive, from program-inhibit voltage provisioning means (250) a program inhibit voltage (GND), and to provide to the corresponding word line said program inhibit voltage (GND) when the word line is unselected during the program operation, first biasing means (220,225) for driving the second biasing circuit path in order to control a conduction state thereof; wherein: said first biasing circuit path includes a first transistor (M2) controlled to be electrically conductive when the corresponding word line is selected, and to be electrically non-conductive when the corresponding word line is unselected; said first biasing means controls the second biasing circuit path to be conductive when, during the program operation, the corresponding word line is unselected, said second biasing circuit path includes a plurality of series connected transistors, a number of transistors in said plurality being at least equal to the smallest integer not less than an absolute value of a ratio between a voltage equal to the difference between the programming voltage and the program-inhibit voltage to a predetermined maximum voltage given by the maximum voltage which a transistor of said series-connected transistors can sustain before it breaks down.

Abstract translation: 一种用于半导体存储器的行选择器，包括耦合到对应的多个字线的多个存储器单元，所述行选择器包括：对于每个字线：适于偏置相应字词的第一偏置电路路径（230; 215; 260） 当选择所述对应的字线用于在耦合到对应字线的至少一个存储单元上选择性地执行编程操作时，所述第一偏置电路路径包括编程电压提供装置（215），其适于提供编程电压 ; 第二偏置电路路径（235），其适于从编程禁止电压供应装置（250）接收编程禁止电压（GND），并且在所述字处理时向所述对应字线提供所述编程禁止电压（GND） 在程序操作期间，线路未选择，用于驱动第二偏置电路路径的第一偏置装置（220,225），以便控制其导通状态; 其中：所述第一偏置电路路径包括当选择相应的字线时被控制为导电的第一晶体管（M2），并且当相应的字线未被选择时是不导电的; 当编程操作期间相应的字线未选择时，所述第一偏置装置控制第二偏置电路路径导通，所述第二偏置电路路径包括多个串联连接的晶体管，所述多个晶体管中的多个晶体管至少为 等于最小整数，其不小于等于编程电压与编程禁止电压之差的电压与由所述串联晶体管的晶体管的最大电压给定的预定最大电压之间的比率的绝对值 在它崩溃之前可以维持。

公开(公告)号：EP1403880B1

公开(公告)日：2007-05-23

申请号：EP02425593.7

申请日：2002-09-30

Applicant: STMicroelectronics S.r.l.

Inventor： Campardo, Giovanni ,  Micheloni, Rino

IPC: G11C29/00

CPC classification number: G11C29/82 ,  G11C29/02 ,  G11C29/025 ,  G11C29/50008 ,  G11C29/83 ,  G11C29/832

公开(公告)号：EP1750277A1

公开(公告)日：2007-02-07

申请号：EP05425559.1

申请日：2005-07-28

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Bovino, Angelo ,  Ravasio, Roberto ,  Micheloni, Rino

IPC: G11C11/56 ,  G11C16/20

CPC classification number: G11C11/5621 ,  G11C16/20

Abstract: A multilevel flash memory device of enhanced performance allows for a faster and more effective configuration of the operating parameters of the memory device, for performing the different functioning algorithms of the memory in the most efficient manner as possible.
The identification of an optimal configuration of the operating parameters of the memory device during testing is simplified by allowing for a one-time processing of configuration bits into "algorithm-friendly" data that are stored in a purposely embedded ancillary random access memory at every power-on of the memory device by executing a specific power-on algorithm code stored in the ancillary read only memory of the embedded microprocessor.
The ancillary random access memory capable of storing processed configuration data permits a further simplification and quickening of the trimming operations of the device that are performed during the testing phase of the single device being fabricated, by supporting a enhanced emulation of the many possible configurations and selectable test parameters for identifying optimal configuration and corresponding operating parameters of the memory device, before eventually conditioning (e.g. burning) the corresponding configuration fuses of the fabricated memory device.

Abstract translation: 具有增强性能的多级闪存器件允许更快更有效地配置存储器件的操作参数，以尽可能以最有效的方式执行存储器的不同功能算法。 通过允许将配置位一次性处理成“算法友好”数据来简化在测试期间存储器件的操作参数的最佳配置，每个功率存储在有意嵌入的辅助随机存取存储器中 - 通过执行存储在嵌入式微处理器的辅助只读存储器中的特定加电算法代码来存储存储器件。 能够存储经处理的配置数据的辅助随机存取存储器允许进一步简化和加快在制造的单个设备的测试阶段期间执行的设备的修整操作，通过支持许多可能配置的增强仿真并且可选择 在最终调节（例如燃烧）所制造的存储器件的相应配置保险丝之前，用于识别存储器件的最佳配置和相应操作参数的测试参数。

公开(公告)号：EP1729302A1

公开(公告)日：2006-12-06

申请号：EP05104656.3

申请日：2005-05-31

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Crippa, Luca ,  Ragone, Giancarlo ,  Sangalli, Miriam ,  Micheloni, Rino

IPC: G11C11/56 ,  G11C16/28 ,  G11C16/30

CPC classification number: G11C11/5642 ,  G11C7/04 ,  G11C16/30

Abstract: A circuit comprises at least one memory cell ( 110 ) adapted to store data in terms of values of an electrical characteristic thereof, which exhibits a variability with temperature according to a first variation law; a voltage generator ( 300 ) is provided for generating a voltage (Vo) to be supplied to the at least one memory cell ( 110 ) for retrieving the data stored therein, the voltage generator including first means ( 305 ) adapted to cause the generated voltage take a value in a set of target values including at least one target value (Vr-1,Vr-2,Vr-3,Vfy-1,Vfy-2,Vfy-3), corresponding to an operation to be performed on the memory cell. The voltage generator comprises second means ( Mt,Rs,325, R1,R2,330 ) for causing the value taken by the generated voltage vary with temperature according to a prescribed second variation law exploiting a compensation circuit element ( Mt ) having said electrical characteristic.

Abstract translation: 电路包括至少一个存储单元（110），其适于根据其电特性的值存储数据，其根据第一变化规律表现出与温度的变化性; 提供电压发生器（300），用于产生要提供给所述至少一个存储单元（110）的电压（Vo），用于检索存储在其中的数据，所述电压发生器包括第一装置（305），其适于使所产生的电压 在包含至少一个目标值（Vr-1，Vr-2，Vr-3，Vfy-1，Vfy-2，Vfy-3）的目标值集合中取值， 记忆单元 电压发生器包括用于使所产生的电压所采用的值根据规定的第二变化规律随温度变化的第二装置（Mt，Rs，325，R1，R2,330），该规定的第二变化规律利用具有所述电特性的补偿电路元件 。