公开(公告)号：JPS62210693A

公开(公告)日：1987-09-16

申请号：JP5260486

申请日：1986-03-12

Applicant: TOSHIBA CORP

Inventor： SAITO MASAYUKI ,  OHIRA HIROSHI ,  YOSHIDA KENICHI

IPC: H05K3/46

公开(公告)号：JPS62210691A

公开(公告)日：1987-09-16

申请号：JP5260286

申请日：1986-03-12

Applicant: TOSHIBA CORP

Inventor： NIITSUMA AKIRA ,  SAITO MASAYUKI ,  OHIRA HIROSHI

IPC: H05K3/46

公开(公告)号：JPS62164737A

公开(公告)日：1987-07-21

申请号：JP411586

申请日：1986-01-14

Applicant: TOSHIBA CORP

Inventor： IIDA ATSUKO ,  SAITO MASAYUKI

IPC: C08J7/00 ,  B29C35/08 ,  B29C59/16 ,  H05K1/03 ,  H05K3/00

Abstract: PURPOSE:To perform processing of increased elaborateness and good reproducibility in processing part of an organic polymer, by selectively irradiating the area to be processed with laser beams and removing organic polymer on an unirradiated area by heating or etching. CONSTITUTION:In processing pattof an organic polymer, an organic polymer on an area to be processed is irradiated selectively with laser beams. Then an organic polymer on an unirradiated area is removed by heating or etching. It is desirable that an excimer laser is used as said laser beams. When polytetrafluoroethylene or thermosetting 1,2-polybutadiene resin is used as said organic polymer, said processing is highly effective because such resins can hardly be processed otherwise.

公开(公告)号：JPS62130592A

公开(公告)日：1987-06-12

申请号：JP26937285

申请日：1985-12-02

Applicant: TOSHIBA CORP

Inventor： SAITO MASAYUKI ,  NIITSUMA AKIRA ,  OHIRA HIROSHI

IPC: H05K3/10 ,  H05K3/20

公开(公告)号：JPS6151905A

公开(公告)日：1986-03-14

申请号：JP17438784

申请日：1984-08-22

Applicant: Toshiba Corp

Inventor： SAITO MASAYUKI ,  OHIRA HIROSHI

IPC: H01G4/12 ,  H01G4/06 ,  H01G4/08

公开(公告)号：JP2000268702A

公开(公告)日：2000-09-29

申请号：JP7116999

申请日：1999-03-17

Applicant: TOSHIBA CORP

Inventor： MORI MIKI ,  HARA YUJIRO ,  YAMAMOTO MASAHIKO ,  FUKUDA YUMI ,  ITO TAKESHI ,  SAITO MASAYUKI ,  FUKUDA KATSUYOSHI ,  ASAI HIRONORI

IPC: H01J9/02 ,  H01J1/304

Abstract: PROBLEM TO BE SOLVED: To implement field emission at a low voltage by making close a distance between a gate and an emitter with the center of an emitter electrode portion having a more recessed shape than its periphery. SOLUTION: A recessed portion having a depth of 0.5-0.3 μm is formed by etching at a cathode wiring 2 portion of a substrate having an insulation characteristic at its surface and being made of glass or the like, then an Mo is formed by sputtering, and patterning is performed, thereby forming a cathode wiring 2. Nextly, an interlayer insulation film 6 for performing insulation between the wiring 2 and gate wiring 8 is formed of SiO2, or the like with a thickness of about 800 nm, and thereon the wiring 8 is applied with pattering of Ni with a thickness of 1 μm by electroless plating of Ni-P type. Then, the wiring 2 is exposed by etching the film 6 of an emmitter formation part, dispersion liquid having ethanol as dispersant while containing CBN fine particles is dropped thereon so that the surface is made recessed. Thereafter, after a solvent is volatiled, thermal treatment is applied thereto to fix the Mo and CBN of the wiring 2 to use is as an eanitter, which is made close to the wiring 8.

公开(公告)号：JPH11259448A

公开(公告)日：1999-09-24

申请号：JP6344098

申请日：1998-03-13

Applicant: TOSHIBA CORP

Inventor： SHIRATORI MASAYUKI ,  SAITO MASAYUKI ,  SHIMADA HIDEKI

IPC: G06F19/00 ,  G06F17/00 ,  G06Q10/00 ,  G06Q50/00 ,  G06Q50/10

Abstract: PROBLEM TO BE SOLVED: To provide an environment influence evaluation table assuming/evaluating influence given to an environment from harmfulness and usefulness when technology to be researched is completed, and to provide a computer system for generating the evaluation table and outputting an evaluation result using the evaluation table. SOLUTION: This table has a column for evaluating an evaluation result with respect to a plurality of evaluation items on harmfulness and usefulness when development completes, an entry column for a point obtained by multiplying the evaluation value and the weight points of the respective items, a total column into which the total of the points of the respective items is filled, a column which judges the total number of the evaluation result and into which 'significance' or 'no' is written, the content filling column of 'presence' against harmfulness or usefulness and a progress report column. This evaluation system has information 32 on the evaluation item and information 33 of evaluation reference. A generation supporting means 41 generates evaluation information 31 of research/development technology where a generation supporting means 41 becomes object based on information. An evaluation means 42 automatically executes evaluation on generated evaluation information 31 and the result is added to evaluation information 31. Evaluation information is outputted in the environment influence evaluation table and in the other system.

公开(公告)号：JPH1098044A

公开(公告)日：1998-04-14

申请号：JP24824296

申请日：1996-09-19

Applicant: TOSHIBA CORP

Inventor： YAMADA HIROSHI ,  HIGUCHI KAZUTO ,  SAITO MASAYUKI

IPC: H01L21/60 ,  B23K35/22 ,  H01L21/321 ,  H05K1/09

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device, a circuit wiring substrate and a structure with a semiconductor device mounted thereon, having bump electrode structure of high reliability. SOLUTION: A semiconductor device is provided with a semiconductor chip 1, bonding pads 2 formed on the semiconductor chip 1, and bump electrodes 8 on the bonding pads 2. The bump electrode 8 includes a first metal layer 4 formed on the bonding pads 2, a second metal layer 5 formed on the first metal layer 4, and a third metal layer 7 formed on the second metal layer 5 and connected to a circuit wiring substrate. Further, in proximity to the interface between the second metal layer 5 and the third metal layer 7, there is a concentrated region wherein at least one kind of element selected among a group of carbon, sulfur and oxygen is dispersed at a concentration higher than that of the internal region 6 of the second metal layer.

公开(公告)号：JPH1092868A

公开(公告)日：1998-04-10

申请号：JP24740696

申请日：1996-09-19

Applicant: TOSHIBA CORP

Inventor： HIGUCHI KAZUTO ,  MIYAGI TAKESHI ,  SAITO MASAYUKI ,  IZEKI YUJI ,  HANAWA TAKESHI

IPC: H01L21/60

Abstract: PROBLEM TO BE SOLVED: To attain cheap and good antenna characteristics, without using complicated manufacturing process by providing partly removed ground conductors on a first surface and microstrip antenna on a second surface. SOLUTION: The device comprises a semiconductor chip 6 and TAB film carrier tape 2 with a microstrip antenna. The chip 6 has an r-f integrated circuit on the surface of a GaAs substrate. This circuit has strip conductor lines and circuit elements, including semiconductor elements, capacitors and inductors. The tape 2 uses a double layer wiring tape having circular patches 1 of radiating conductor on one surface and ground conductor plane 9 on the other surface. The gap 8 is located on the top face of a microstrip line 13 to be a feed line on the chip 6 and the feed line is electromagnetically coupled with the conductor 1 through the gap 8.

公开(公告)号：JPH1079403A

公开(公告)日：1998-03-24

申请号：JP23517796

申请日：1996-09-05

Applicant: TOSHIBA CORP

Inventor： HONMA SOICHI ,  YAMADA HIROSHI ,  SAITO MASAYUKI

IPC: H01L21/60 ,  H01L23/12

Abstract: PROBLEM TO BE SOLVED: To simplify the process for manufacturing a semiconductor device by a method, wherein first connection pads are provided on the surface of a semiconductor chip, a first insulating layer is formed on the region of the chip excluding the connection pads and a second insulating layer, barrier metal layers, conductive bonding meterial layers, second connection pads, and a wiring board are sequentially formed on the first insulating layer. SOLUTION: First connection pads 2 are provided on the surface of a semiconductor chip 1 and a first insulating layer 3 is formed on the region of the chip 1, excluding the pads 2. A second insulating layer 4 having openings on the pads 2 is formed on the layer 3 and, at the same time, recessed part-shaped barrier metal layers 5 are formed on the pads 2 and the inner walls of the openings. Conductive bonding material layers 8 are made to be bonded to the interiors of recessed parts formed in the layers 5, and a wiring board 6 is provided on the layers 8 via second connection pads 7. Thereby the process for manufacturing a semiconductor device is made simple, and the cost of the device can be reduced.