中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

124 records (took 0.028 seconds)

    Semiconductor structure and process thereof
    81.
    发明授权
    Semiconductor structure and process thereof 有权
    半导体结构及其工艺

    公开(公告)号：US09093285B2

    公开(公告)日：2015-07-28

    申请号：US13848736

    申请日：2013-03-22

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Po-Chao Tsao

    IPC: H01L27/108 ,  H01L27/06 ,  H01L21/28 ,  H01L49/02 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

    CPC classification number: H01L27/0629 ,  H01L21/28 ,  H01L21/76802 ,  H01L21/76877 ,  H01L27/1085 ,  H01L28/60 ,  H01L28/75 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/66477 ,  H01L29/66545

    Abstract: A semiconductor structure includes a metal gate, a second dielectric layer and a contact plug. The metal gate is located on a substrate and in a first dielectric layer, wherein the metal gate includes a work function metal layer having a U-shaped cross-sectional profile and a low resistivity material located on the work function metal layer. The second dielectric layer is located on the metal gate and the first dielectric layer. The contact plug is located on the second dielectric layer and in a third dielectric layer, thereby a capacitor is formed. Moreover, the present invention also provides a semiconductor process forming said semiconductor structure.

    Abstract translation: 半导体结构包括金属栅极，第二电介质层和接触插塞。 金属栅极位于基板和第一电介质层中，其中金属栅极包括具有U形横截面轮廓的功函数金属层和位于功函数金属层上的低电阻率材料。 第二电介质层位于金属栅极和第一电介质层上。 接触塞位于第二电介质层上，在第三电介质层中形成电容器。 此外，本发明还提供了形成所述半导体结构的半导体工艺。

    Manufacturing method for forming a self aligned contact
    82.
    发明授权
    Manufacturing method for forming a self aligned contact 有权
    用于形成自对准接触的制造方法

    公开(公告)号：US08993433B2

    公开(公告)日：2015-03-31

    申请号：US13902977

    申请日：2013-05-27

    Applicant: United Microelectronics Corp.

    Inventor： Chieh-Te Chen ,  Yu-Tsung Lai ,  Hsuan-Hsu Chen ,  Feng-Yi Chang ,  Chih-Sen Huang ,  Ching-Wen Hung

    IPC: H01L21/4763 ,  H01L21/44 ,  H01L21/768

    CPC classification number: H01L21/76816 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485

    Abstract: The present invention provides a manufacturing method of a semiconductor device, at least containing the following steps: first, a substrate is provided, wherein a first dielectric layer is formed on the substrate, at least one metal gate is formed in the first dielectric layer and at least one source drain region (S/D region) is disposed on two sides of the metal gate, at least one first trench is then formed in the first dielectric layer, exposing parts of the S/D region. The manufacturing method for forming the first trench further includes performing a first photolithography process through a first photomask and performing a second photolithography process through a second photomask, and at least one second trench is formed in the first dielectric layer, exposing parts of the metal gate, and finally, a conductive layer is filled in each first trench and each second trench.

    Abstract translation: 本发明提供一种半导体器件的制造方法，至少包括以下步骤：首先，提供基板，其中在基板上形成第一介电层，在第一介电层中形成至少一个金属栅极， 至少一个源极漏极区域（S / D区域）设置在金属栅极的两侧，然后在第一介电层中形成至少一个第一沟槽，暴露S / D区域的部分。 用于形成第一沟槽的制造方法还包括通过第一光掩模执行第一光刻工艺并通过第二光掩模执行第二光刻工艺，并且在第一电介质层中形成至少一个第二沟槽，暴露部分金属栅极 并且最后，在每个第一沟槽和每个第二沟槽中填充导电层。

    Method for Forming Semiconductor Structure Having Opening
    83.
    发明申请
    Method for Forming Semiconductor Structure Having Opening 审中-公开
    形成具有开口的半导体结构的方法

    公开(公告)号：US20140342553A1

    公开(公告)日：2014-11-20

    申请号：US13893349

    申请日：2013-05-14

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chieh-Te Chen ,  Feng-Yi Chang ,  Hsuan-Hsu Chen ,  Yu-Tsung Lai ,  Chih-Sen Huang ,  Ching-Wen Hung

    IPC: H01L21/768 ,  H01L21/283

    CPC classification number: H01L21/76897 ,  H01L21/31144 ,  H01L21/76816

    Abstract: According to one embodiment of the present invention, a method for forming a semiconductor structure having an opening is provided. First, a substrate is provided, wherein a first region and a second region are defined on the substrate and an overlapping area of the first region and the second region is defined as a third region. Then, a material layer is formed on the substrate. A first hard mask and a second hard mask are formed on the material layer. The first hard mask in the first region is removed to form a patterned first hard mask. The second hard mask in the third region is removed to form a patterned second hard mask. Lastly, the material layer is patterned by using the patterned second hard mask layer as a mask to form at least an opening in the third region only.

    Abstract translation: 根据本发明的一个实施例，提供一种形成具有开口的半导体结构的方法。 首先，提供衬底，其中在衬底上限定第一区域和第二区域，并且将第一区域和第二区域的重叠区域定义为第三区域。 然后，在基板上形成材料层。 第一硬掩模和第二硬掩模形成在材料层上。 第一区域中的第一硬掩模被去除以形成图案化的第一硬掩模。 去除第三区域中的第二硬掩模以形成图案化的第二硬掩模。 最后，通过使用图案化的第二硬掩模层作为掩模来对材料层进行图案化，以仅在第三区域中形成至少一个开口。

    Semiconductor fin-shaped structure and manufacturing process thereof
    84.
    发明授权
    Semiconductor fin-shaped structure and manufacturing process thereof 有权
    半导体鳍状结构及其制造工艺

    公开(公告)号：US08802521B1

    公开(公告)日：2014-08-12

    申请号：US13909101

    申请日：2013-06-04

    Applicant: United Microelectronics Corp.

    Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Shih-Fang Hong

    IPC: H01L21/336 ,  H01L29/06 ,  H01L21/762

    CPC classification number: H01L21/76224 ,  H01L21/3086 ,  H01L29/6681 ,  H01L29/7851

    Abstract: The present invention provides a method for forming a fin structure comprising the following steps: first, a substrate is provided and a plurality of fin structures, a plurality of first dummy fin structures and a plurality of second dummy fin structures are formed on the substrate; a first patterned photoresist is used as a hard mask to perform a first etching process to remove each first dummy fin structure; then a second patterned photoresist is used as a hard mask to perform a second etching process to remove each second dummy fin structure, wherein the pattern density of the first patterned photoresist is higher than the pattern density of the second patterned.

    Abstract translation: 本发明提供一种形成翅片结构的方法，包括以下步骤：首先，提供基板，并在基板上形成多个翅片结构，多个第一虚拟翅片结构和多个第二虚拟翅片结构; 使用第一图案化的光致抗蚀剂作为硬掩模来执行第一蚀刻工艺以去除每个第一虚拟鳍结构; 然后使用第二图案化的光刻胶作为硬掩模来执行第二蚀刻工艺以去除每个第二虚拟鳍片结构，其中第一图案化光刻胶的图案密度高于第二图案化图案的图案密度。

    METHOD OF FORMING SEMICONDUCTOR STRUCTURE HAVING CONTACT PLUG
    85.
    发明申请
    METHOD OF FORMING SEMICONDUCTOR STRUCTURE HAVING CONTACT PLUG 有权
    形成具有接触片的半导体结构的方法

    公开(公告)号：US20140199837A1

    公开(公告)日：2014-07-17

    申请号：US13740289

    申请日：2013-01-14

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ching-Wen Hung ,  En-Chiuan Liou ,  Chih-Sen Huang ,  Po-Chao Tsao

    IPC: H01L21/768

    CPC classification number: H01L21/76816 ,  H01L21/28518 ,  H01L21/31144 ,  H01L21/76814 ,  H01L21/76855 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of forming a semiconductor structure having at least a contact plug includes the following steps. At first, at least a transistor and an inter-layer dielectric (ILD) layer are formed on a substrate, and the transistor includes a gate structure and two source/drain regions. Subsequently, a cap layer is formed on the ILD layer and on the transistor, and a plurality of openings that penetrate through the cap layer and the ILD layer until reaching the source/drain regions are formed. Afterward, a conductive layer is formed to cover the cap layer and fill the openings, and a part of the conductive layer is further removed for forming a plurality of first contact plugs, wherein a top surface of a remaining conductive layer and a top surface of a remaining cap layer are coplanar, and the remaining cap layer totally covers a top surface of the gate structure.

    Abstract translation: 形成至少具有接触插塞的半导体结构的方法包括以下步骤。 首先，在衬底上形成至少一个晶体管和层间电介质（ILD）层，并且晶体管包括栅极结构和两个源极/漏极区域。 随后，在ILD层和晶体管上形成覆盖层，并且形成穿过覆盖层和ILD层的多个开口直到到达源/漏区。 之后，形成导电层以覆盖盖层并填充开口，并且进一步去除导电层的一部分以形成多个第一接触塞，其中剩余导电层的顶表面和顶表面 剩余的盖层是共面的，剩余的盖层完全覆盖栅极结构的顶表面。

Patent Agency Ranking