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    Method of depositing polysilicon, method of fabricating a field effect transistor, method of forming a contact to a substrate, method of forming a capacitor
    81.
    发明授权
    Method of depositing polysilicon, method of fabricating a field effect transistor, method of forming a contact to a substrate, method of forming a capacitor 失效
    沉积多晶硅的方法，制造场效应晶体管的方法，与衬底形成接触的方法，形成电容器的方法

    公开(公告)号：US6159852A

    公开(公告)日：2000-12-12

    申请号：US23239

    申请日：1998-02-13

    Applicant: Michael Nuttall ,  Er-Xuan Ping ,  Yongjun Jeff Hu

    Inventor： Michael Nuttall ,  Er-Xuan Ping ,  Yongjun Jeff Hu

    IPC: C23C16/04 ,  C23C16/24 ,  H01L21/285 ,  H01L21/768 ,  H01L29/417 ,  H01L29/78 ,  H01L21/4763

    CPC classification number: H01L29/41783 ,  C23C16/04 ,  C23C16/24 ,  H01L21/28525 ,  H01L21/28562 ,  H01L21/76879 ,  H01L29/41775 ,  H01L29/7834

    Abstract: In a method of depositing polysilicon comprises providing a substrate within a chemical vapor deposition reactor, with the substrate having an exposed substantially crystalline region and an exposed substantially amorphous region. A gaseous precursor comprising silicon is fed to the chemical vapor deposition reactor under conditions effective to selectively deposit polysilicon on the crystalline region and not the amorphous region. In another aspect a method of fabricating a field effect transistor on a substrate comprises forming a gate dielectric layer and a gate over semiconductive material. A gaseous precursor comprising silicon is fed to the chemical vapor deposition reactor under conditions effective to substantially selectively deposit polysilicon on the source/drain regions and not on amorphous material, and forming elevated source/drains on the doped source/drain regions. In another aspect, a method of forming a contact to a substrate is disclosed. A contact opening is etched through amorphous insulating material over a node location ultimately comprising an outwardly exposed substantially crystalline surface. Within a chemical vapor deposition reactor, a gaseous precursor comprising silicon is provided under conditions effective to selectively deposit polysilicon on the outwardly exposed crystalline node location surface and not on the insulating material.

    Abstract translation: 在沉积多晶硅的方法中包括在化学气相沉积反应器内提供衬底，其中衬底具有暴露的基本上结晶的区域和暴露的基本非晶区域。 包含硅的气体前体在有效选择性地在结晶区域而非非晶区域上沉积多晶硅的条件下进料至化学气相沉积反应器。 在另一方面，在衬底上制造场效应晶体管的方法包括形成栅极介电层和半导体材料上的栅极。 包含硅的气体前体在有效基本上选择性地在源极/漏极区域上而不是无定形材料上沉积多晶硅并且在掺杂源极/漏极区域上形成升高的源极/漏极的条件下被馈送到化学气相沉积反应器。 另一方面，公开了一种形成与基板的接触的方法。 接触开口在最终包括向外暴露的基本上结晶的表面的节点位置上通过非晶绝缘材料蚀刻。 在化学气相沉积反应器内，在有效选择性地将多晶硅沉积在外露的晶体结点位置表面而不是在绝缘材料上的条件下提供了包含硅的气态前体。

    Methods of forming CoSi2, methods of forming field effect transistors, and methods of forming conductive contacts
    86.
    发明授权
    Methods of forming CoSi2, methods of forming field effect transistors, and methods of forming conductive contacts 有权
    形成CoSi2的方法，形成场效应晶体管的方法以及形成导电触点的方法

    公开(公告)号：US08435889B2

    公开(公告)日：2013-05-07

    申请号：US13182285

    申请日：2011-07-13

    Applicant: Yongjun Jeff Hu

    Inventor： Yongjun Jeff Hu

    IPC: H01L21/28 ,  H01L29/43

    CPC classification number: H01L29/665 ,  H01L21/28518

    Abstract: The invention included to methods of forming CoSi2, methods of forming field effect transistors, and methods of forming conductive contacts. In one implementation, a method of forming CoSi2 includes forming a substantially amorphous layer comprising MSix over a silicon-containing substrate, where “M” comprises at least some metal other than cobalt. A layer comprising cobalt is deposited over the substantially amorphous MSix-comprising layer. The substrate is annealed effective to diffuse cobalt of the cobalt-comprising layer through the substantially amorphous MSix-comprising layer and combine with silicon of the silicon-containing substrate to form CoSi2 beneath the substantially amorphous MSix-comprising layer. Other aspects and implementations are contemplated.

    Abstract translation: 本发明包括形成CoSi 2的方法，形成场效应晶体管的方法以及形成导电触点的方法。 在一个实施方案中，形成CoSi 2的方法包括在含硅衬底上形成包含MSix的基本非晶层，其中“M”至少包括除钴以外的一些金属。 包含钴的层沉积在基本上无定形的含MSix的层上。 将衬底退火有效地将含钴层的钴扩散通过基本上无定形的含MSix层并与含硅衬底的硅结合，以在基本上无定形的含MSix层下形成CoSi 2。 考虑了其他方面和实现。

    METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING DIFFUSION REGIONS OF REDUCED WIDTH
    87.
    发明申请
    METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING DIFFUSION REGIONS OF REDUCED WIDTH 有权
    形成具有减小宽度扩散区域的半导体器件的方法

    公开(公告)号：US20120329258A1

    公开(公告)日：2012-12-27

    申请号：US13604411

    申请日：2012-09-05

    Applicant: Lequn Liu ,  Yongjun Jeff Hu ,  Anish A. Khandekar

    Inventor： Lequn Liu ,  Yongjun Jeff Hu ,  Anish A. Khandekar

    IPC: H01L21/265

    CPC classification number: H01L21/2652 ,  H01L21/26513 ,  H01L27/11526 ,  H01L27/11548 ,  H01L29/6659 ,  H01L29/66659

    Abstract: Semiconductor devices and methods for forming semiconductor devices are provided, including semiconductor devices that comprise one or more diffusion region in a semiconductor, the one or more diffusion regions being adjacent to a gate formed adjacent to a surface of the semiconductor (e.g., a semiconductor substrate). The one or more diffusion regions comprise a first width at a depth below the surface of the semiconductor and a second width near the surface of the semiconductor, the second width of the one or more diffusion regions being less than about 40% greater than the first width.

    Abstract translation: 提供了用于形成半导体器件的半导体器件和方法，包括在半导体中包括一个或多个扩散区的半导体器件，所述一个或多个扩散区与邻近半导体表面形成的栅极（例如，半导体衬底 ）。 一个或多个扩散区域包括在半导体表面下方的深度处的第一宽度和靠近半导体表面的第二宽度，一个或多个扩散区域的第二宽度小于第一宽度的大约40％ 宽度。

    Semiconductor devices and methods of forming semiconductor devices having diffusion regions of reduced width
    88.
    发明授权
    Semiconductor devices and methods of forming semiconductor devices having diffusion regions of reduced width 有权
    形成半导体器件的半导体器件和方法，该半导体器件具有减小宽度的扩散区域

    公开(公告)号：US08283708B2

    公开(公告)日：2012-10-09

    申请号：US12562635

    申请日：2009-09-18

    Applicant: Lequn Liu ,  Yongjun Jeff Hu ,  Anish A. Khandekar

    Inventor： Lequn Liu ,  Yongjun Jeff Hu ,  Anish A. Khandekar

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L21/2652 ,  H01L21/26513 ,  H01L27/11526 ,  H01L27/11548 ,  H01L29/6659 ,  H01L29/66659

    Abstract: Semiconductor devices and methods for forming semiconductor devices are provided, including semiconductor devices that comprise one or more diffusion region in a semiconductor, the one or more diffusion regions being adjacent to a gate formed adjacent to a surface of the semiconductor (e.g., a semiconductor substrate). The one or more diffusion regions comprise a first width at a depth below the surface of the semiconductor and a second width near the surface of the semiconductor, the second width of the one or more diffusion regions being less than about 40% greater than the first width.

    Abstract translation: 提供了用于形成半导体器件的半导体器件和方法，包括在半导体中包括一个或多个扩散区的半导体器件，所述一个或多个扩散区与邻近半导体表面形成的栅极（例如，半导体衬底 ）。 一个或多个扩散区域包括在半导体表面下方的深度处的第一宽度和靠近半导体表面的第二宽度，一个或多个扩散区域的第二宽度小于第一宽度的大约40％ 宽度。

    Methods Of Forming Doped Regions In Semiconductor Substrates
    89.
    发明申请
    Methods Of Forming Doped Regions In Semiconductor Substrates 有权
    在半导体衬底中形成掺杂区域的方法

    公开(公告)号：US20120108042A1

    公开(公告)日：2012-05-03

    申请号：US12938845

    申请日：2010-11-03

    Applicant: Jennifer Lequn Liu ,  Shu Qin ,  Allen McTeer ,  Yongjun Jeff Hu

    Inventor： Jennifer Lequn Liu ,  Shu Qin ,  Allen McTeer ,  Yongjun Jeff Hu

    IPC: H01L21/322

    CPC classification number: H01L21/2236 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/26526 ,  H01L29/66575

    Abstract: Some embodiments include methods of forming one or more doped regions in a semiconductor substrate. Plasma doping may be used to form a first dopant to a first depth within the substrate. The first dopant may then be impacted with a second dopant to knock the first dopant to a second depth within the substrate. In some embodiments the first dopant is p-type (such as boron) and the second dopant is neutral type (such as germanium). In some embodiments the second dopant is heavier than the first dopant.

    Abstract translation: 一些实施例包括在半导体衬底中形成一个或多个掺杂区域的方法。 可以使用等离子体掺杂来形成第一掺杂剂到衬底内的第一深度。 然后可以用第二掺杂剂冲击第一掺杂剂以将第一掺杂剂敲入衬底内的第二深度。 在一些实施方案中，第一掺杂剂是p型（例如硼），第二掺杂剂是中性型（例如锗）。 在一些实施方案中，第二掺杂剂比第一掺杂剂重。

    SEMICONDUCTOR DEVICES AND METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING DIFFUSION REGIONS OF REDUCED WIDTH
    90.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING DIFFUSION REGIONS OF REDUCED WIDTH 有权
    半导体器件和形成具有减小宽度扩散区域的半导体器件的方法

    公开(公告)号：US20110068378A1

    公开(公告)日：2011-03-24

    申请号：US12562635

    申请日：2009-09-18

    Applicant: Lequn Liu ,  Yongjun Jeff Hu ,  Anish A. Khandekar

    Inventor： Lequn Liu ,  Yongjun Jeff Hu ,  Anish A. Khandekar

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L21/2652 ,  H01L21/26513 ,  H01L27/11526 ,  H01L27/11548 ,  H01L29/6659 ,  H01L29/66659

    Abstract: Semiconductor devices and methods for forming semiconductor devices are provided, including semiconductor devices that comprise one or more diffusion region in a semiconductor, the one or more diffusion regions being adjacent to a gate formed adjacent to a surface of the semiconductor (e.g., a semiconductor substrate). The one or more diffusion regions comprise a first width at a depth below the surface of the semiconductor and a second width near the surface of the semiconductor, the second width of at the one or more diffusion regions being less than about 40% greater than the first width.

    Abstract translation: 提供了用于形成半导体器件的半导体器件和方法，包括在半导体中包括一个或多个扩散区的半导体器件，所述一个或多个扩散区与邻近半导体表面形成的栅极（例如，半导体衬底 ）。 一个或多个扩散区域包括在半导体表面下方的深度处的第一宽度和靠近半导体表面的第二宽度，在一个或多个扩散区域处的第二宽度小于大约40％ 第一宽

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