Multi-layer via-less thin film resistor and manufacturing method therefor
    6.
    发明公开
    Multi-layer via-less thin film resistor and manufacturing method therefor 审中-公开
    MehrschichtigerDünnfilmwiderstandohneKontaktlöcherund Herstellungsverfahrendafür

    公开(公告)号:EP2423949A2

    公开(公告)日:2012-02-29

    申请号:EP11178593.7

    申请日:2011-08-24

    Abstract: The present disclosure is directed to a thin film resistor (102) having a first resistor layer (103a) having a first temperature coefficient of resistance and a second resistor layer (103b) on the first resistor layer, the second resistor layer having a second temperature coefficient of resistance different from the first temperature coefficient of resistance. The first temperature coefficient of resistance may be positive while the second temperature coefficient of resistance is negative. The first resistor layer may have a thickness in the range of 5-15 nm and the second resistor layer may have a thickness in the range of 2-5 nm.

    Abstract translation: 本公开涉及一种薄膜电阻器(102),其具有第一电阻层(103a)和第二电阻层(103b),第一电阻层(103a)具有第一温度系数电阻,第二电阻层具有第二温度 电阻系数与第一温度系数电阻不同。 电阻的第一温度系数可以为正,而第二温度系数为负。 第一电阻层的厚度可以在5-15nm的范围内,第二电阻层的厚度可以在2-5nm的范围内。

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