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    Electrical test method for printed circuit board
    3.
    发明专利
    Electrical test method for printed circuit board 审中-公开
    印刷电路板电气测试方法

    公开(公告)号：JP2005024338A

    公开(公告)日：2005-01-27

    申请号：JP2003188272

    申请日：2003-06-30

    Applicant: Brain Power Co ,  欣強科技股▲ふん▼有限公司

    Inventor： SU SUNG-LENG

    IPC: G01R31/02 ,  H05K3/00

    Abstract: PROBLEM TO BE SOLVED: To provide an electrical test method for a printed circuit board actualized by a dedicated-type tester through the manufacture of conductive rubber and a printed circuit board of a special shape, and solving a problem wherein measurement of high-degree analysis on a minute circuit has not been performed by a known measurement method using the short-circuiting and circuit cutting of a printed circuit board, as to an electrical test method for a printed circuit board utilizing conductive rubber.
    SOLUTION: This electrical test method for a printed circuit board is actualized by the dedicated-type tester through the manufacture of the conductive rubber and the printed circuit board of a special shape. Further, a defect is eliminated that measurement of high-degree analysis on a minute circuit has been impossible by a known measurement method using the short-circuiting and circuit cutting of a printed circuit board.
    COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：为了提供通过专用型测试仪通过制造导电橡胶和特殊形状的印刷电路板实现的印刷电路板的电气测试方法，并且解决了高的测量 对于使用导电橡胶的印刷电路板的电气测试方法，通过使用印刷电路板的短路和电路切割的已知测量方法未对分钟电路进行分析。

    解决方案：通过专用型测试仪通过制造导电橡胶和特殊形状的印刷电路板，实现了印刷电路板的这种电气测试方法。 此外，消除了通过使用印刷电路板的短路和电路切割的已知测量方法来测量微小电路的高度分析的缺陷。 版权所有（C）2005，JPO＆NCIPI

    Process for producing buried thin film resistor of printed board
    4.
    发明专利
    Process for producing buried thin film resistor of printed board 审中-公开
    生产印刷板的薄膜薄膜电阻的方法

    公开(公告)号：JP2005332870A

    公开(公告)日：2005-12-02

    申请号：JP2004147854

    申请日：2004-05-18

    Applicant: Brain Power Co ,  欣強科技股▲ふん▼有限公司

    Inventor： SU SUNG-LENG ,  XU ZHIQIANG

    IPC: H05K1/16 ,  H01C7/00 ,  H01C17/06 ,  H01C17/22

    Abstract: PROBLEM TO BE SOLVED: To provide a process for producing a buried thin film resistor of a printed board. SOLUTION: A resistor layer is formed in a printed board having a conductive circuit in order to save the space for arranging a resistor in the board thus reducing the size of the board. Capacitance effect of pins at the opposite ends of a traditional resistor is reduced in order to enhance the speed and quality of signal transmission. It can be completed by a traditional production facility of printed board without purchasing a new facility and has advantages of mass production and reduction in production cost. COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：提供一种用于制造印刷电路板的埋入薄膜电阻器的方法。 解决方案：在具有导电电路的印刷电路板中形成电阻层，以便节省用于在电路板上布置电阻器的空间，从而减小电路板的尺寸。 降低传统电阻器相对端的引脚的电容效应，以提高信号传输的速度和质量。 可以通过印刷电路板的传统生产设施完成，而不需要购买新的设备，并具有批量生产和降低生产成本的优点。 版权所有（C）2006，JPO＆NCIPI

    Memory module not storing parity bits
    5.
    发明专利
    Memory module not storing parity bits 未知

    公开(公告)号：GB2283340A

    公开(公告)日：1995-05-03

    申请号：GB9322190

    申请日：1993-10-28

    Applicant: BRAIN POWER CO

    Inventor： CHAN JAMES

    IPC: G06F11/10

    Abstract: A memory module (20, Fig 3) contains a memory checker 50, which comprises a parity checker 51, a single bit storage 52 and a parity generator 53. Parity bits of incoming data are not stored, and parity bits for outgoing data are generated from the data by parity generator 53. If the parity bit of an incoming data byte is incorrect, the bit in storage 52 is set, whereby the calculated parity bit for the next outgoing byte is deliberately made incorrect; this causes an external parity checker (40) to generate a parity error interrupt (43).

    NEW MEMORY CHECKER
    7.
    发明专利
    NEW MEMORY CHECKER 未知

    公开(公告)号：GB9322190D0

    公开(公告)日：1993-12-15

    申请号：GB9322190

    申请日：1993-10-28

    Applicant: BRAIN POWER CO

    IPC: G06F11/10

    Abstract: A new memory checker comprised of a parity checker (51), a bit storage (52), and a parity generator (53), and installed in the memory module (20) of a computer system (10) for checking data error, wherein the parity checker (51) receives the data bus and input parity signal from the computer system (10) to check out error from the data been fetched from the memory module (20) and then to provide an interrupt signal (43) to the computer system (10) upon the checking of an error.

    Memory checking circuit
    8.
    发明专利
    Memory checking circuit 未知

    公开(公告)号：DE4335604A1

    公开(公告)日：1995-04-20

    申请号：DE4335604

    申请日：1993-10-19

    Applicant: BRAIN POWER CO

    Inventor： CHAN JAMES

    IPC: G06F11/10

    Abstract: The memory checking circuit has a parity checking circuit (51), a bit memory (52) and a parity generator (53) and is integrated in the memory module (20) of a computer system (10) for the purpose of determining data errors; the computer (10) feeds data on the data bus (31) and the parity signal (32) to the parity checking circuit (51) in order to determine errors in the data read from the memory module (20) and, once an error has been established, to generate an interrupt signal (43) which is fed to the computer (10).

    Parity bit memory simulator
    9.
    发明公开
    Parity bit memory simulator 失效
    Paritätsbit-Speichersimulator

    公开(公告)号：EP0717356A1

    公开(公告)日：1996-06-19

    申请号：EP94119647.9

    申请日：1994-12-13

    Applicant: BRAIN POWER CO.

    Inventor： Chan, James

    IPC: G06F11/10

    CPC classification number: G06F11/1032

    Abstract: A parity bit memory simulator including a parity bit memory formed of a single bit memory of fixed address length, which replaces the single bit parity RAM of variable address length of conventional memory module, and connected with its address signal line to the data bus of the memory module so that the parity bit memory provides and store parity bits for the computer system without changing the circuit layout of the data memory or caring about the capacity of the memory module. A voltage level detector and a refreshing operation detector can be installed in the parity bit memory to improve the error detecting function of the dynamic random access memory module in the parity bit system.

    Abstract translation: 一种奇偶校验位存储器模拟器，包括由固定地址长度的单位存储器形成的奇偶校验位存储器，其替代常规存储器模块的可变地址长度的单位奇偶校验RAM，并将其地址信号线连接到数据总线 使得奇偶校验位存储器为计算机系统提供和存储奇偶校验位，而不改变数据存储器的电路布局或关心存储器模块的容量。 可以在奇偶校验位存储器中安装电压电平检测器和刷新操作检测器，以改进奇偶校验位系统中的动态随机存取存储器模块的错误检测功能。

    Method for fabricating embedded thin film resistors
    10.
    发明公开
    Method for fabricating embedded thin film resistors 有权
    一种用于制造嵌入薄膜电阻器的方法

    公开(公告)号：EP1592289A1

    公开(公告)日：2005-11-02

    申请号：EP05009384.8

    申请日：2005-04-28

    Applicant: Brain Power Co.

    Inventor： Su, Sung-Ling ,  Xu, Zhiqiang

    IPC: H05K1/16 ,  H05K3/18

    CPC classification number: H05K1/167 ,  H05K3/061 ,  H05K3/181 ,  H05K3/184 ,  H05K2201/0391 ,  H05K2203/0361 ,  H05K2203/1453

    Abstract: A method for fabricating the embedded thin film resistors of a printed circuit board is provided. The embedded thin film resistors are formed using a resistor layer built in the printed circuit board. Compared with conventional discrete resistors, embedded thin film resistors contribute to a smaller printed circuit board as the space for installing conventional resistors is saved, and better signal transmission speed and quality as the capacitive reactance effect caused by two connectors of the conventional resistors is avoided. The method for fabricating the embedded thin film resistors provided by the invention can be conducted using the process and equipment for conventional printed circuit boards and thereby saving the investment on new types of equipment. The method can be applied in the mass production of printed circuit boards and thereby reduce the manufacturing cost significantly.

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