公开(公告)号：WO2005013348A2

公开(公告)日：2005-02-10

申请号：PCT/US2004/024595

申请日：2004-07-30

Applicant: TOKYO ELECTRON LIMITED ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  O'MEARA, David, L. ,  WAJDA, Cory ,  DIP, Anthony ,  TOELLER, Michael ,  FURUKAWA, Toshihara ,  SCHEER, Kristen ,  CALLEGARI, Alessandro ,  BUEHRER, Fred ,  ZAFAR, Sufi ,  GOUSEV, Evgeni ,  CHOU, Anthony ,  HIGGINS, Paul

Inventor： O'MEARA, David, L. ,  WAJDA, Cory ,  DIP, Anthony ,  TOELLER, Michael ,  FURUKAWA, Toshihara ,  SCHEER, Kristen ,  CALLEGARI, Alessandro ,  BUEHRER, Fred ,  ZAFAR, Sufi ,  GOUSEV, Evgeni ,  CHOU, Anthony ,  HIGGINS, Paul

IPC: H01L21/314

CPC classification number: H01L21/67098 ,  H01L21/0214 ,  H01L21/02238 ,  H01L21/02249 ,  H01L21/02255 ,  H01L21/3144 ,  H01L21/31604 ,  H01L21/31616 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31662

Abstract: Ultra-thin oxide and oxynitride layers are formed utilizing low pressure processing to achieve self-limiting oxidation of substrates and provide ultra-thin oxide and oxynitride. The substrates to be processed can contain an initial dielectric layer such as an oxide layer, an oxynitride layer, a nitride layer, a high-k layer, or alternatively can lack an initial dielectric layer. The processing can be carried out using a batch type process chamber or, alternatively, using a single-wafer process chamber. One embodiment of the invention provides self-limiting oxidation of Si-substrates that results in Si0 2 layers with a thickness of about 15Å, where the thickness of the Si0 2 layers varies less than about 1 Åover the substrates.

Abstract translation: 使用低压处理形成超薄氧化物和氧氮化物层，以实现衬底的自限制氧化并提供超薄氧化物和氧氮化物。 待处理的基板可以包含初始介电层，例如氧化物层，氧氮化物层，氮化物层，高k层，或者可以缺少初始介电层。 处理可以使用间歇式处理室进行，或者使用单晶圆处理室进行。 本发明的一个实施例提供Si衬底的自限制氧化，其导致SiO 2层的厚度为约15，其中SiO 2层的厚度在基板之外变化小于约1埃。

公开(公告)号：WO2006076086A3

公开(公告)日：2009-04-16

申请号：PCT/US2005043552

申请日：2005-12-02

Applicant: IBM ,  CALLEGARI ALESSANDRO C ,  GRIBELYUK MICHAEL A ,  LACEY DIANNE L ,  MCFEELY FENTON R ,  SAENGER KATHERINE L ,  ZAFAR SUFI

Inventor： CALLEGARI ALESSANDRO C ,  GRIBELYUK MICHAEL A ,  LACEY DIANNE L ,  MCFEELY FENTON R ,  SAENGER KATHERINE L ,  ZAFAR SUFI

IPC: H01L29/94 ,  H01L29/76 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/4966 ,  C23C14/0036 ,  C23C14/0635 ,  H01L21/28088 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665

Abstract: A compound metal comprising TiC which is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as well as a method of fabricating the TiC compound metal. Furthermore, the TiC metal compound of the present invention is a very efficient oxygen diffusion barrier at 1000°C allowing very aggressive equivalent oxide thickness (EOT) and inversion layer thickness scaling below 14 Å in a p-metal oxide semiconductor (pMOS) device.

Abstract translation: 提供了包含TiC的复合金属，其是在包括高k电介质和界面层的栅极堆叠上具有约4.75至约5.3，优选约5e的功函数的功函数的热电稳定的p型金属，以及 制造TiC复合金属的方法。 此外，本发明的TiC金属化合物在1000℃下是非常有效的氧扩散阻挡层，在p-金属氧化物半导体（pMOS）器件中允许非常有侵蚀性的等效氧化物厚度（EOT）和低于14的反型层厚度标度。

公开(公告)号：WO2006076086A2

公开(公告)日：2006-07-20

申请号：PCT/US2005/043552

申请日：2005-12-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  CALLEGARI, Alessandro C. ,  GRIBELYUK, Michael A. ,  LACEY, Dianne L. ,  MCFEELY, Fenton R. ,  SAENGER, Katherine L. ,  ZAFAR, Sufi

Inventor： CALLEGARI, Alessandro C. ,  GRIBELYUK, Michael A. ,  LACEY, Dianne L. ,  MCFEELY, Fenton R. ,  SAENGER, Katherine L. ,  ZAFAR, Sufi

IPC: H01L29/94 ,  H01L29/76 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/4966 ,  C23C14/0036 ,  C23C14/0635 ,  H01L21/28088 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665

Abstract: A compound metal comprising TiC which is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as well as a method of fabricating the TiC compound metal. Furthermore, the TiC metal compound of the present invention is a very efficient oxygen diffusion barrier at 1000°C allowing very aggressive equivalent oxide thickness (EOT) and inversion layer thickness scaling below 14 Å in a p-metal oxide semiconductor (pMOS) device.

Abstract translation: 提供了包含TiC的复合金属，其是具有约4.75至约5.3，优选约5e的功函数的p型金属，其在包含高k电介质和界面层的栅叠层上是热稳定的，以及 制造TiC复合金属的方法。 此外，本发明的TiC金属化合物在1000℃下是非常有效的氧扩散阻挡层，允许在p-金属氧化物半导体（pMOS）器件中具有非常强大的等效氧化物厚度（EOT）和反型层厚度缩小至14以下。

公开(公告)号：WO2005013348A3

公开(公告)日：2005-09-22

申请号：PCT/US2004024595

申请日：2004-07-30

Applicant: TOKYO ELECTRON LTD ,  IBM ,  O'MEARA DAVID L ,  WAJDA CORY ,  DIP ANTHONY ,  TOELLER MICHAEL ,  FURUKAWA TOSHIHARA ,  SCHEER KRISTEN ,  CALLEGARI ALESSANDRO ,  BUEHRER FRED ,  ZAFAR SUFI ,  GOUSEV EVGENI ,  CHOU ANTHONY ,  HIGGINS PAUL

Inventor： O'MEARA DAVID L ,  WAJDA CORY ,  DIP ANTHONY ,  TOELLER MICHAEL ,  FURUKAWA TOSHIHARA ,  SCHEER KRISTEN ,  CALLEGARI ALESSANDRO ,  BUEHRER FRED ,  ZAFAR SUFI ,  GOUSEV EVGENI ,  CHOU ANTHONY ,  HIGGINS PAUL

IPC: H01L21/00 ,  H01L21/314 ,  H01L21/316 ,  C23C16/30 ,  C23C16/40 ,  C23C16/44 ,  C23C16/455 ,  H01L21/318

CPC classification number: H01L21/67098 ,  H01L21/0214 ,  H01L21/02238 ,  H01L21/02249 ,  H01L21/02255 ,  H01L21/3144 ,  H01L21/31604 ,  H01L21/31616 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31662

Abstract: Ultra-thin oxide and oxynitride layers are formed utilizing low pressure processing to achieve self-limiting oxidation of substrates and provide ultra-thin oxide and oxynitride. The substrates to be processed can contain an initial dielectric layer such as an oxide layer, an oxynitride layer, a nitride layer, a high-k layer, or alternatively can lack an initial dielectric layer. The processing can be carried out using a batch type process chamber or, alternatively, using a single-wafer process chamber. One embodiment of the invention provides self-limiting oxidation of Si-substrates that results in Si02 layers with a thickness of about 15Å, where the thickness of the Si02 layers varies less than about 1 Åover the substrates.

Abstract translation: 使用低压处理形成超薄氧化物和氮氧化物层以实现衬底的自限氧化并提供超薄氧化物和氮氧化物。 待处理的衬底可以包含诸如氧化物层，氮氧化物层，氮化物层，高k层的初始电介质层，或者可替代地可以缺少初始电介质层。 该处理可以使用批量式处理室或者使用单晶片处理室来进行。 本发明的一个实施方案提供了Si-衬底的自限氧化，其导致厚度为约的SiO 2层，其中SiO 2层的厚度在衬底上的变化小于约1。

公开(公告)号：WO2005047561A1

公开(公告)日：2005-05-26

申请号：PCT/EP2004/052927

申请日：2004-11-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  NARAYANAN, Vijay ,  MCFEELY, Fenton ,  MILKOVE, Keith, Raymond ,  YURKAS, John, Jacob ,  COPEL, Matthew, Warren ,  JAMISON, Paul, Charles ,  CARRUTHERS, Roy ,  CABRAL JNR, Cyril ,  SIKORSKI, Edmund ,  DUCH, Elizabeth ,  CALLEGARI, Alessandro ,  ZAFAR, Sufi ,  NAKAMURA, Kazuhito

Inventor： NARAYANAN, Vijay ,  MCFEELY, Fenton ,  MILKOVE, Keith, Raymond ,  YURKAS, John, Jacob ,  COPEL, Matthew, Warren ,  JAMISON, Paul, Charles ,  CARRUTHERS, Roy ,  CABRAL JNR, Cyril ,  SIKORSKI, Edmund ,  DUCH, Elizabeth ,  CALLEGARI, Alessandro ,  ZAFAR, Sufi ,  NAKAMURA, Kazuhito

IPC: C23C16/34

CPC classification number: C23C16/34 ,  H01L21/28088 ,  H01L21/823828 ,  H01L29/4966 ,  H01L29/78

Abstract: Compounds of Ta and N, potentially including further elements, and with a resistivity below about 20mΩcm and with the elemental ratio of N to Ta greater than about 0.9 are disclosed for use as gate materials in field effect devices. A representative embodiment of such compounds, TaSiN, is stable at typical CMOS processing temperatures on SiO 2 containing dielectric layers and high-k dielectric layers, with a workfunction close to that of n-type Si. Metallic Ta - N compounds are deposited by a chemical vapor deposition method using an alkylimidotris(dialkylamido)Ta species, such as tertiaryamylimidotris(dimethylamido)Ta (TAIMATA), as Ta precursor. The deposition is conformal allowing for flexible introduction of the Ta-N metallic compounds into a CMOS processing flow. Devices processed with TaN or TaSiN show near ideal characteristics.

Abstract translation: 公开了用于场效应装置中的栅极材料的Ta和N的化合物，潜在地包括其它元素，电阻率低于约20mohmcm，并且N与Ta的元素比大于约0.9。 这种化合物的典型实施方案TaSiN在典型的CMOS处理温度下对含SiO 2的电介质层和高k电介质层是稳定的，功函数接近n型Si的功函数。 金属Ta-N化合物通过化学气相沉积法使用烷基亚氨基三（二烷基酰氨基）Ta物质如叔戊酰亚氨基三（二甲基酰氨基）Ta（TAIMATA））作为Ta前体沉积。 沉积是共形的，允许将Ta-N金属化合物柔性引入CMOS加工流程。 用TaN或TaSiN处理的器件显示出接近理想的特性。

公开(公告)号：WO2008098890A1

公开(公告)日：2008-08-21

申请号：PCT/EP2008/051595

申请日：2008-02-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  ZAFAR, Sufi ,  CALLEGARI, Alessandro ,  CHUDZIK, Michael, Patrick ,  NARAYANAN, Vijay ,  PARUCHURI, Vamsi ,  LINDER, Barry, Paul ,  PARK, Dae-Gyu ,  MO, Renee, Tong

Inventor： ZAFAR, Sufi ,  CALLEGARI, Alessandro ,  CHUDZIK, Michael, Patrick ,  NARAYANAN, Vijay ,  PARUCHURI, Vamsi ,  LINDER, Barry, Paul ,  PARK, Dae-Gyu ,  MO, Renee, Tong

IPC: H01L21/28 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L21/28088 ,  H01L21/28518 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665

Abstract: A multilayered gate stack having improved reliability (i.e., low charge trapping and gate leakage degradation) is provided. The inventive multilayered gate stack includes, from bottomto top, a metal nitrogen-containing layer located on a surface of a high-k gate dielectric and Si-containing conductor located directly on a surface of the metal nitrogen-containing layer. The improved reliability is achieved by utilizing a metal nitrogen-containing layer having a compositionalratioofmetal to nitrogen of less than 1.1. The inventive gate stack can be useful as an element of a complementary metal oxide semiconductor (CMOS). The present invention also provides a method of fabricating such a gate stack in which the process conditions of a sputtering process are varied to control the ratio ofmetaland nitrogen within the sputter deposited layer.

Abstract translation: 提供了具有改进的可靠性（即，低电荷捕获和栅极泄漏劣化）的多层栅极堆叠。 本发明的多层栅极堆叠包括位于位于金属含氮层的表面上的高k栅极电介质和含Si导体的表面上的含氮金属层的底部至顶部。 通过利用具有低于1.1的金属与氮的组成的金属含氮层来实现提高的可靠性。 本发明的栅叠层可用作互补金属氧化物半导体（CMOS）的元件。 本发明还提供一种制造这种栅极堆叠的方法，其中溅射工艺的工艺条件被改变以控制溅射沉积层内的金属和氮的比例。

公开(公告)号：WO2006076087A3

公开(公告)日：2006-07-20

申请号：PCT/US2005/043555

申请日：2005-12-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  CALLEGARI, Alessandro C. ,  FRANK, Martin M. ,  JAMMY, Rajarao ,  LACEY, Dianne L. ,  MCFEELY, Fenton R. ,  ZAFAR, Sufi

Inventor： CALLEGARI, Alessandro C. ,  FRANK, Martin M. ,  JAMMY, Rajarao ,  LACEY, Dianne L. ,  MCFEELY, Fenton R. ,  ZAFAR, Sufi

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/336

Abstract: A compound metal comprising HfSiN which is a n-type metal having a workfunction of about 4.0 to about 4.5, preferably about 4.3, eV which is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer. Furthermore, after annealing the stack of HfSiN/high k dielectric/interfacial layer at a high temperature (on the order of about 1000°C), there is a reduction of the interfacial layer, thus the gate stack produces a very small equivalent oxide thickness (12 Å classical), which cannot be achieved using TaSiN.

公开(公告)号：WO2006076087A2

公开(公告)日：2006-07-20

申请号：PCT/US2005043555

申请日：2005-12-02

Applicant: IBM ,  CALLEGARI ALESSANDRO C ,  FRANK MARTIN M ,  JAMMY RAJARAO ,  LACEY DIANNE L ,  MCFEELY FENTON R ,  ZAFAR SUFI

Inventor： CALLEGARI ALESSANDRO C ,  FRANK MARTIN M ,  JAMMY RAJARAO ,  LACEY DIANNE L ,  MCFEELY FENTON R ,  ZAFAR SUFI

IPC: H01L29/94

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659

Abstract: A compound metal comprising HfSiN which is a n-type metal having a workfunction of about 4.0 to about 4.5, preferably about 4.3, eV which is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer. Furthermore, after annealing the stack of HfSiN/high k dielectric/interfacial layer at a high temperature (on the order of about 1000°C), there is a reduction of the interfacial layer, thus the gate stack produces a very small equivalent oxide thickness (12 Å classical), which cannot be achieved using TaSiN.

Abstract translation: 包含HfSiN的复合金属，其是具有约4.0至约4.5，优选约4.3的功函数的n型金属，其在包含高k电介质和界面层的栅极堆叠上是热稳定的。 此外，在高温（约1000℃）的高温下退火HfSiN /高k电介质/界面层之后，界面层的减少，因此栅叠层产生非常小的等效氧化物厚度 （12经典），使用TaSiN无法实现。

公开(公告)号：WO2005029568A3

公开(公告)日：2005-03-31

申请号：PCT/US2004/026811

申请日：2004-08-19

Applicant: TOKYO ELECTRON LIMITED ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  O'MEARA, David, L. ,  WAJDA, Cory ,  TAKAHASHI, Tsuyoshi ,  CALLEGARI, Alessandro ,  SCHEER, Kristen ,  ZAFAR, Sufi ,  JAMISON, Paul

Inventor： O'MEARA, David, L. ,  WAJDA, Cory ,  TAKAHASHI, Tsuyoshi ,  CALLEGARI, Alessandro ,  SCHEER, Kristen ,  ZAFAR, Sufi ,  JAMISON, Paul

IPC: H01L21/314

Abstract: A method is provided for forming a microstructure with an interfacial oxide layer by using a diffusion filter layer to control the oxidation properties of a substrate associated with formation of a high-k layer into the microstructure. The diffusion filter layer controls the oxidation of the surface. The interfacial oxide layer can be formed during an oxidation process that is carried out following deposition of a high­k layer onto the diffusion filter layer, or during deposition of a high-k layer onto the diffusion filter layer.

公开(公告)号：WO2011023519A1

公开(公告)日：2011-03-03

申请号：PCT/EP2010/061403

申请日：2010-08-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  CALLEGARI, Alessandro ,  BABICH, Katherina ,  O'SULLIVAN, Eugene ,  CONNOLLY, John

Inventor： CALLEGARI, Alessandro ,  BABICH, Katherina ,  O'SULLIVAN, Eugene ,  CONNOLLY, John

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76879 ,  H01J37/3045 ,  H01J37/305 ,  H01J37/3056 ,  H01L23/53276 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of selectively growing one or more carbon nano-tubes includes forming an insulating layer (10) on a Substrate (12), the insulating layer having a top surface (14); forming a via (18) in the insulating layer; forming an active metal layer (30) over the insulating layer, including sidewall and bottom surfaces of the via; and removing the active metal layer at portions of the top surface with an ion beam to enable the selective growth of one or more carbon nano-tubes inside the via.

Abstract translation: 选择性地生长一个或多个碳纳米管的方法包括在基板（12）上形成绝缘层（10），所述绝缘层具有顶表面（14）; 在绝缘层中形成通孔（18）; 在所述绝缘层上形成活性金属层（30），包括所述通孔的侧壁和底表面; 并且用离子束在顶表面的部分去除活性金属层，以使一个或多个碳纳米管在通孔内部选择性地生长。