公开(公告)号：WO2009090517A2

公开(公告)日：2009-07-23

申请号：PCT/IB2008/055565

申请日：2008-12-29

Applicant: NXP B.V. ,  DE VRIES, Dirk, Kenneth

Inventor： DE VRIES, Dirk, Kenneth

IPC: H01L23/544

CPC classification number: H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention relates to a chain test structure with first pattern of electrically conductive segments on a first level, a second pattern of electrically conductive segments on a second level at a larger distance from the substrate than the first level, a via pattern with via elements, which respectively connect selected pairs of the first and second segments to form a series connection of first and second segments that alternates between the first and the second levels, and -a third pattern of conductive segments on a third level, which third pattern repeats the second pattern of the second segments. The third segments are connected with their respective corresponding second segment by at least one respective via pair to form respective parallel connections of pairs of one second and one corresponding third conductive segment. The chain test structure allows a precise measurement of a contact or via fail rate.

Abstract translation: 本发明涉及一种链测试结构，其具有在第一水平上的导电段的第一图案，在第二水平上的距离衬底比第一水平更大距离处的导电区段的第二图案，具有通孔元件的通孔图案 ，其分别连接所选择的第一和第二段对，以形成在第一和第二水平之间交替的第一和第二段的串联连接，以及在第三水平上的第三图案的导电段，该第三图案重复 第二段的第二模式。 第三段通过至少一个相应的通孔对与其相应的对应的第二段连接，以形成一对第二和第一对应的第三导电段的对的并联连接。 链式测试结构允许精确测量接触或通过故障率。

公开(公告)号：WO2006123281A1

公开(公告)日：2006-11-23

申请号：PCT/IB2006/051495

申请日：2006-05-12

Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  DE VRIES, Dirk, Kenneth

Inventor： DE VRIES, Dirk, Kenneth

IPC: G01R31/28

CPC classification number: G01R31/2884 ,  G01R1/0408

Abstract: A test structure (32) for detecting the presence of defects in conductive features formed on integrated circuit topography, which is configured for both voltage contrast inspectability and electrical measurability. A comb- like structure comprising pairs of adjacent conductive lines (22) is provided on a first side of an insulating (dielectric) layer provided on a substrate, each pair of lines (22) being selectively connectable at one end to ground (GND). Floating conductive lines (14) are provided in between the lines (22). Each pair of conductive lines (22) is connected together at the other end thereof by a conductive connecting piece (30), by means of respective vias (28) provided through the insulating layer, to provide a serpentine structure to support electrical measurement of opens. The ends of the floating lines (14) are connected to a conductive spine (18) on the other side of the insulating layer, by means of respective vias (16) provided through the insulating layer to provide a conductive comb- like structure to support electrical measurement of shorts.

Abstract translation: 一种用于检测在集成电路形貌上形成的导电特征中的缺陷的存在的测试结构（32），其被配置用于电压对比度检查和电可测量性。 在设置在基板上的绝缘（电介质）层的第一侧上设置包括一对相邻的导线（22）的梳状结构，每对线（22）可以在一端可选地连接到地（GND） 。 浮线（14）设置在线（22）之间。 每对导电线（22）的另一端通过导电连接片（30），通过穿过绝缘层提供的相应的通路（28）连接在一起，以提供蛇形结构，以支持开路的电测量 。 浮动线（14）的端部通过穿过绝缘层提供的相应的通路（16）连接到绝缘层的另一侧上的导电脊（18），以提供导电梳状结构以支撑 短路电气测量。

公开(公告)号：WO2009090517A3

公开(公告)日：2009-09-11

申请号：PCT/IB2008055565

申请日：2008-12-29

Applicant: NXP BV ,  DE VRIES DIRK KENNETH

Inventor： DE VRIES DIRK KENNETH

IPC: H01L23/544

CPC classification number: H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention relates to a chain test structure with first pattern of electrically conductive segments on a first level, a second pattern of electrically conductive segments on a second level at a larger distance from the substrate than the first level, a via pattern with via elements, which respectively connect selected pairs of the first and second segments to form a series connection of first and second segments that alternates between the first and the second levels, and -a third pattern of conductive segments on a third level, which third pattern repeats the second pattern of the second segments. The third segments are connected with their respective corresponding second segment by at least one respective via pair to form respective parallel connections of pairs of one second and one corresponding third conductive segment. The chain test structure allows a precise measurement of a contact or via fail rate.

Abstract translation: 本发明涉及一种链式测试结构，其具有第一层上的导电段的第一图案，第二层上的导电段的第二图案，与第一层相比距离衬底更大的距离，具有过孔元件的过孔图案 ，其分别连接第一和第二段的选定对以形成在第一和第二层之间交替的第一和第二段的串联连接，以及 - 第三层上的第三导电段的图案，该第三图案重复 第二部分的第二模式。 第三段通过至少一个相应的通孔对与它们各自相应的第二段连接，以形成一对第二和一个对应的第三导电段的各自的并联连接。 链式测试结构允许精确测量接触或通过故障率。

公开(公告)号：WO2008052940A3

公开(公告)日：2008-07-03

申请号：PCT/EP2007061537

申请日：2007-10-26

Applicant: KONINKL PHILIPS ELECTRONICS NV ,  ST MICROELECTRONICS CROLLES 2 ,  DE VRIES DIRK KENNETH ,  GONELLA ROBERTO MAURIZIO

Inventor： DE VRIES DIRK KENNETH ,  GONELLA ROBERTO MAURIZIO

IPC: H01L23/544

CPC classification number: G01R31/2884 ,  G01R31/2831 ,  H01L22/34 ,  H01L2924/3011

Abstract: The present invention relates to a test structure that comprises at least two devices under test DUT, which respectively have a first electrical device resistance in a non- defect state and a second electrical device resistance in defect state, the first being higher than the second electrical device resistance. In the test structure the DUTs are connected in parallel to a first test contact pad via a first conducting line and connected in parallel to a second test contact pad via a second conducting line, and respectively connected to the first conducting line via respective first test resistors, which have known respective electrical test resistances, such that a total electrical resistance between the first an second test contact pads is indicative of the number of DUTs, which have the second electrical device resistance. The test structure allows testing a larger number of DUTs in parallel in a single measurement.

Abstract translation: 本发明涉及一种测试结构，其包括至少两个被测器件DUT，其分别具有处于非缺陷状态的第一电器件电阻和处于缺陷状态的第二电器件电阻，所述第一电器件电阻高于第二电器 器件电阻。 在测试结构中，DUT经由第一导线与第一测试接触焊盘并联连接并且经由第二导线与第二测试接触焊盘并联连接，并且经由第一测试电阻器分别连接到第一导线 ，其具有各自的电测试电阻，使得第一和第二测试接触垫之间的总电阻指示具有第二电装置电阻的DUT的数量。 测试结构允许在单次测量中并行测试大量DUT。

公开(公告)号：WO2008052940A2

公开(公告)日：2008-05-08

申请号：PCT/EP2007/061537

申请日：2007-10-26

Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  ST MICROELECTRONICS (CROLLES 2) SAS ,  DE VRIES, Dirk Kenneth ,  GONELLA, Roberto Maurizio

Inventor： DE VRIES, Dirk Kenneth ,  GONELLA, Roberto Maurizio

CPC classification number: G01R31/2884 ,  G01R31/2831 ,  H01L22/34 ,  H01L2924/3011

Abstract: The present invention relates to a test structure that comprises at least two devices under test DUT, which respectively have a first electrical device resistance in a non- defect state and a second electrical device resistance in defect state, the first being higher than the second electrical device resistance. In the test structure the DUTs are connected in parallel to a first test contact pad via a first conducting line and connected in parallel to a second test contact pad via a second conducting line, and respectively connected to the first conducting line via respective first test resistors, which have known respective electrical test resistances, such that a total electrical resistance between the first an second test contact pads is indicative of the number of DUTs, which have the second electrical device resistance. The test structure allows testing a larger number of DUTs in parallel in a single measurement.

Abstract translation: 本发明涉及一种测试结构，该测试结构包括至少两个被测试器件，它们分别具有处于非缺陷状态的第一电子器件电阻和处于缺陷状态的第二电子器件电阻，第一器件电阻高于第二电气 器件电阻。 在测试结构中，DUT通过第一导电线并联连接到第一测试接触焊盘，并经由第二导线并联连接到第二测试接触焊盘，并且经由相应的第一测试电阻器分别连接到第一导线 其已知各自的电测试电阻，使得第一和第二测试接触焊盘之间的总电阻指示具有第二电气设备电阻的DUT的数量。 测试结构允许在单次测量中并行测试更多的DUT。

公开(公告)号：WO2006033073A1

公开(公告)日：2006-03-30

申请号：PCT/IB2005/053073

申请日：2005-09-19

Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  DE VRIES, Dirk Kenneth ,  VAN DE GOOR, Albert

Inventor： DE VRIES, Dirk Kenneth ,  VAN DE GOOR, Albert

IPC: H01L23/544 ,  H01L21/66

CPC classification number: H01L22/34 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A method of obtaining parametric test data for use in monitoring alignment between layers of a semiconductor device. The method employs a test structure comprising a meander (10, 30) of the material of a first layer of the semiconductor device, deposited relative to a conductive line (18,38). A number of sets (16a, 16b, 16e, 16d) of components 16, such as contacts or vias, are provided relative to the meander (10), at successively smaller distances therefrom. A single analogue measurement can be performed between a first end (A) of the meander (10, 30) and the conductive line (18, 38) so as to determine the resistance therebetween, and the critical distance at (or on acceptable margin in relation thereto) between the first layer and a component of the semiconductor device can be obtained.

Abstract translation: 一种获得用于监测半导体器件的层之间的对准的参数测试数据的方法。 该方法采用包括相对于导电线（18,38）沉积的半导体器件的第一层的材料的曲折（10,30）的测试结构。 相对于曲折件（10），在与其相距较小的距离处提供多个组件16的组（16a，16b，16e，16d），例如触点或通孔。 可以在曲折（10,30）的第一端（A）和导线（18,38）之间进行单个模拟测量，以便确定它们之间的电阻，以及在（或可接受的边缘）处的临界距离 可以获得第一层和半导体器件的成分之间的关​​系。