公开(公告)号：WO2008052940A2

公开(公告)日：2008-05-08

申请号：PCT/EP2007/061537

申请日：2007-10-26

Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  ST MICROELECTRONICS (CROLLES 2) SAS ,  DE VRIES, Dirk Kenneth ,  GONELLA, Roberto Maurizio

Inventor： DE VRIES, Dirk Kenneth ,  GONELLA, Roberto Maurizio

CPC classification number: G01R31/2884 ,  G01R31/2831 ,  H01L22/34 ,  H01L2924/3011

Abstract: The present invention relates to a test structure that comprises at least two devices under test DUT, which respectively have a first electrical device resistance in a non- defect state and a second electrical device resistance in defect state, the first being higher than the second electrical device resistance. In the test structure the DUTs are connected in parallel to a first test contact pad via a first conducting line and connected in parallel to a second test contact pad via a second conducting line, and respectively connected to the first conducting line via respective first test resistors, which have known respective electrical test resistances, such that a total electrical resistance between the first an second test contact pads is indicative of the number of DUTs, which have the second electrical device resistance. The test structure allows testing a larger number of DUTs in parallel in a single measurement.

Abstract translation: 本发明涉及一种测试结构，该测试结构包括至少两个被测试器件，它们分别具有处于非缺陷状态的第一电子器件电阻和处于缺陷状态的第二电子器件电阻，第一器件电阻高于第二电气 器件电阻。 在测试结构中，DUT通过第一导电线并联连接到第一测试接触焊盘，并经由第二导线并联连接到第二测试接触焊盘，并且经由相应的第一测试电阻器分别连接到第一导线 其已知各自的电测试电阻，使得第一和第二测试接触焊盘之间的总电阻指示具有第二电气设备电阻的DUT的数量。 测试结构允许在单次测量中并行测试更多的DUT。

公开(公告)号：WO2006069982A1

公开(公告)日：2006-07-06

申请号：PCT/EP2005/057150

申请日：2005-12-23

Applicant: STMICROELECTRONICS CROLLES 2 SAS ,  KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  BOROT, Bertrand ,  GONELLA, Roberto, Maurizio ,  FABRE, Sébastien

Inventor： BOROT, Bertrand ,  GONELLA, Roberto, Maurizio ,  FABRE, Sébastien

IPC: H01L23/525

CPC classification number: H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An anti-fuse cell includes a standard MOS transistor of an integrated circuit, with source (7) and drain (8) regions covered with a metal silicide layer (12, 13), and at least one track (24) of a resistive layer at least partially surrounding said MOS transistor, and adapted to pass a heating current such that the metal of said metal silicide diffuses across drain and/or source junctions.

Abstract translation: 反熔丝单元包括集成电路的标准MOS晶体管，源极（7）和漏极（8）区域被金属硅化物层（12,13）覆盖，以及至少一个电阻层的轨道（24） 至少部分地围绕所述MOS晶体管，并且适于通过加热电流，使得所述金属硅化物的金属扩散穿过漏极和/或源极结。

公开(公告)号：WO2008052940A3

公开(公告)日：2008-07-03

申请号：PCT/EP2007061537

申请日：2007-10-26

Applicant: KONINKL PHILIPS ELECTRONICS NV ,  ST MICROELECTRONICS CROLLES 2 ,  DE VRIES DIRK KENNETH ,  GONELLA ROBERTO MAURIZIO

Inventor： DE VRIES DIRK KENNETH ,  GONELLA ROBERTO MAURIZIO

IPC: H01L23/544

CPC classification number: G01R31/2884 ,  G01R31/2831 ,  H01L22/34 ,  H01L2924/3011

Abstract: The present invention relates to a test structure that comprises at least two devices under test DUT, which respectively have a first electrical device resistance in a non- defect state and a second electrical device resistance in defect state, the first being higher than the second electrical device resistance. In the test structure the DUTs are connected in parallel to a first test contact pad via a first conducting line and connected in parallel to a second test contact pad via a second conducting line, and respectively connected to the first conducting line via respective first test resistors, which have known respective electrical test resistances, such that a total electrical resistance between the first an second test contact pads is indicative of the number of DUTs, which have the second electrical device resistance. The test structure allows testing a larger number of DUTs in parallel in a single measurement.

Abstract translation: 本发明涉及一种测试结构，其包括至少两个被测器件DUT，其分别具有处于非缺陷状态的第一电器件电阻和处于缺陷状态的第二电器件电阻，所述第一电器件电阻高于第二电器 器件电阻。 在测试结构中，DUT经由第一导线与第一测试接触焊盘并联连接并且经由第二导线与第二测试接触焊盘并联连接，并且经由第一测试电阻器分别连接到第一导线 ，其具有各自的电测试电阻，使得第一和第二测试接触垫之间的总电阻指示具有第二电装置电阻的DUT的数量。 测试结构允许在单次测量中并行测试大量DUT。