公开(公告)号：WO2006078815A3

公开(公告)日：2006-07-27

申请号：PCT/US2006/001894

申请日：2006-01-18

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  RAO, Satyavolu, Srinivas, Papa ,  CRENSHAW, Darius, Lammont ,  GRUNOW, Stephan ,  BRENNAN, Kenneth, D. ,  JOSHI, Somit ,  LEAVY, Montray ,  MATZ, Phillip, D. ,  AJMERA, Sameer, Kumar ,  SOLOMENTSEV, Yuri, E.

Inventor： RAO, Satyavolu, Srinivas, Papa ,  CRENSHAW, Darius, Lammont ,  GRUNOW, Stephan ,  BRENNAN, Kenneth, D. ,  JOSHI, Somit ,  LEAVY, Montray ,  MATZ, Phillip, D. ,  AJMERA, Sameer, Kumar ,  SOLOMENTSEV, Yuri, E.

IPC: H01L21/20

Abstract: The formation of a MIM (metal insulator metal) capacitor (164) and concurrent formation of a resistor (166) is disclosed. A copper diffusion barrier is formed over a copper deposition (110) that serves as a bottom electrode (170) of the capacitor (164). The copper diffusion barrier mitigates unwanted diffusion of copper from the copper deposition (110), and is formed via electro-less deposition such that little to none of the barrier material is deposited at locations other than over a top surface of the deposition of copper/bottom electrode. Subsequently, layers of dielectric (150) and conductive (152) materials are applied to form a dielectric (172) and top electrode (174) of the MIM capacitor (164), respectively, where the layer of conductive top electrode material (152) also functions to concurrently develop the resistor (166) on the same chip as the capacitor (164).

公开(公告)号：WO2011059827A3

公开(公告)日：2011-05-19

申请号：PCT/US2010/054766

申请日：2010-10-29

Applicant: TOUCHDOWN TECHNOLOGIES, INC. ,  LEAVY, Montray

Inventor： LEAVY, Montray

IPC: H01L21/768

Abstract: Processes are provided herein for the fabrication of MEMS utilizing both a primary metal that is integrated into the final MEMS structure and two or more sacrificial secondary metals that provide structural support for the primary metal component during machining. A first secondary metal is thinly plated around the primarj metal and over the entire surface of the substrate without using photolithography. A second secondary metal, is then thickly plated over the deposited first secondary metal without using photolithography. Additionally, techniques are disclosed to increase the deposition rate of the first secondary metal between primary metal features in order to prevent voiding and thus enhance structural support of the primary metal during machining.

Abstract translation: 这里提供了用于制造利用集成到最终MEMS结构中的主金属和在加工期间为主金属部件提供结构支撑的两种或更多种牺牲次级金属的MEMS的工艺。 第一次级金属在主金属周围以及衬底的整个表面上被薄镀，而不使用光刻法。 然后在没有使用光刻的情况下将第二次级金属厚沉积在沉积的第一次级金属上。 另外，公开了用于增加第一金属特征之间的第一次级金属的沉积速率的技术，以便防止空洞并因此在加工期间增强主金属的结构支撑。

公开(公告)号：WO2008061122A2

公开(公告)日：2008-05-22

申请号：PCT/US2007/084640

申请日：2007-11-14

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  LEAVY, Montray, Cantrell ,  WEST, Jeffrey, Alan ,  MCPHERSON, Kyle, James ,  FAUST, Richard, Allen ,  WU, Lixin

Inventor： LEAVY, Montray, Cantrell ,  WEST, Jeffrey, Alan ,  MCPHERSON, Kyle, James ,  FAUST, Richard, Allen ,  WU, Lixin

IPC: H01L23/52 ,  H01L21/4763

CPC classification number: H01L23/53238 ,  C25D3/38 ,  C25D5/02 ,  C25D5/10 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/76873 ,  H01L21/76877 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor device (100) comprises forming an insulating layer (105) over a semiconductive substrate (110) and forming a copper interconnect. Forming the interconnect includes etching an interconnect opening in the insulating layer and filling the opening with copper plating. Filling with copper plating includes using a first and second electrochemical deposition (ECD). An electrolyte solution of the first and second electrochemical deposition contains organic additives, and a current of the first electrochemical deposition is greater than a current of the second electrochemical deposition.

Abstract translation: 制造半导体器件（100）的方法包括在半导体衬底（110）上形成绝缘层（105）并形成铜互连。 形成互连包括蚀刻绝缘层中的互连开口并用铜电镀填充开口。 填充镀铜包括使用第一和第二电化学沉积（ECD）。 第一和第二电化学沉积物的电解质溶液含有有机添加剂，并且第一电化学沉积的电流大于第二电化学沉积的电流。

公开(公告)号：WO2011059831A2

公开(公告)日：2011-05-19

申请号：PCT/US2010/054793

申请日：2010-10-29

Applicant: TOUCHDOWN TECHNOLOGIES, INC. ,  LEAVY, Montray

Inventor： LEAVY, Montray

CPC classification number: C25D1/003 ,  B32B15/01 ,  C25D3/38

Abstract: Processes are provided herein for the fabrication of MFMS utilizing both a primary metal that is integrated into the final MEMS structure and a sacrificial secondary metal that provides structural support for the primary metal component during machining More specifically, techniques are disclosed to increase the rate of secondary metal deposition between primary metal features in order to prevent voiding in the sacrificial secondary metal and thus enhance structural support of the primary metal during machining.

Abstract translation: 这里提供了利用集成到最终MEMS结构中的主金属和在加工期间为主金属部件提供结构支撑的牺牲次级金属制造MFMS的工艺。更具体地，技术 被公开用于增加主要金属特征之间的次级金属沉积速率，以便防止牺牲次级金属中的空洞并因此加强在加工过程中主要金属的结构支撑。

公开(公告)号：WO2008061122A3

公开(公告)日：2008-07-10

申请号：PCT/US2007084640

申请日：2007-11-14

Applicant: TEXAS INSTRUMENTS INC ,  LEAVY MONTRAY CANTRELL ,  WEST JEFFREY ALAN ,  MCPHERSON KYLE JAMES ,  FAUST RICHARD ALLEN ,  WU LIXIN

Inventor： LEAVY MONTRAY CANTRELL ,  WEST JEFFREY ALAN ,  MCPHERSON KYLE JAMES ,  FAUST RICHARD ALLEN ,  WU LIXIN

IPC: H01L21/44

CPC classification number: H01L23/53238 ,  C25D3/38 ,  C25D5/02 ,  C25D5/10 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/76873 ,  H01L21/76877 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor device (100) comprises forming an insulating layer (105) over a semiconductive substrate (110) and forming a copper interconnect. Forming the interconnect includes etching an interconnect opening in the insulating layer and filling the opening with copper plating. Filling with copper plating includes using a first and second electrochemical deposition (ECD). An electrolyte solution of the first and second electrochemical deposition contains organic additives, and a current of the first electrochemical deposition is greater than a current of the second electrochemical deposition.

Abstract translation: 一种制造半导体器件（100）的方法包括在半导体衬底（110）上形成绝缘层（105）并形成铜互连。 形成互连包括蚀刻绝缘层中的互连开口并用铜电镀填充开口。 填充镀铜包括使用第一和第二电化学沉积（ECD）。 第一和第二电化学沉积物的电解质溶液含有有机添加剂，并且第一电化学沉积的电流大于第二电化学沉积的电流。

公开(公告)号：WO2011059831A3

公开(公告)日：2011-09-01

申请号：PCT/US2010054793

申请日：2010-10-29

Applicant: TOUCHDOWN TECHNOLOGIES INC ,  LEAVY MONTRAY

Inventor： LEAVY MONTRAY

IPC: B81C1/00 ,  B81B3/00 ,  C25D5/02 ,  C25D7/00 ,  G02B26/08 ,  H01H49/00

CPC classification number: C25D1/003 ,  B32B15/01 ,  C25D3/38

Abstract: Processes are provided herein for the fabrication of MFMS utilizing both a primary metal that is integrated into the final MEMS structure and a sacrificial secondary metal that provides structural support for the primary metal component during machining More specifically, techniques are disclosed to increase the rate of secondary metal deposition between primary metal features in order to prevent voiding in the sacrificial secondary metal and thus enhance structural support of the primary metal during machining.

Abstract translation: 本文提供的方法用于利用集成到最终MEMS结构中的主金属和在加工期间为主要金属部件提供结构支撑的牺牲二次金属制造MFMS更具体地，公开了增加次级的速率的技术 金属沉积在主金属特征之间以防止牺牲二次金属中的空隙，从而增强在加工过程中初级金属的结构支撑。

公开(公告)号：WO2011059827A2

公开(公告)日：2011-05-19

申请号：PCT/US2010054766

申请日：2010-10-29

Applicant: TOUCHDOWN TECHNOLOGIES INC ,  LEAVY MONTRAY

Inventor： LEAVY MONTRAY

CPC classification number: C23C28/02 ,  B32B15/01 ,  Y10T428/12229

Abstract: Processes are provided herein for the fabrication of MEMS utilizing both a primary metal that is integrated into the final MEMS structure and two or more sacrificial secondary metals that provide structural support for the primary metal component during machining. A first secondary metal is thinly plated around the primarj metal and over the entire surface of the substrate without using photolithography. A second secondary metal, is then thickly plated over the deposited first secondary metal without using photolithography. Additionally, techniques are disclosed to increase the deposition rate of the first secondary metal between primary metal features in order to prevent voiding and thus enhance structural support of the primary metal during machining.

Abstract translation: 本文提供了用于利用集成到最终MEMS结构中的主金属和在加工期间为主金属部件提供结构支撑的两个或更多个牺牲二次金属来制造MEMS的工艺。 第一二次金属在基底金属周围薄薄地镀覆在衬底的整个表面上，而不使用光刻。 然后将第二二次金属在不使用光刻的情况下在沉积的第一二次金属上进行厚电镀。 此外，公开了增加第一二次金属在主金属特征之间的沉积速率以防止空隙并由此增强在加工期间主金属的结构支撑的技术。

公开(公告)号：WO2006078815A2

公开(公告)日：2006-07-27

申请号：PCT/US2006001894

申请日：2006-01-18

Applicant: TEXAS INSTRUMENTS INC ,  RAO SATYAVOLU SRINIVAS PAPA ,  CRENSHAW DARIUS LAMMONT ,  GRUNOW STEPHAN ,  BRENNAN KENNETH D ,  JOSHI SOMIT ,  LEAVY MONTRAY ,  MATZ PHILLIP D ,  AJMERA SAMEER KUMAR ,  SOLOMENTSEV YURI E

Inventor： RAO SATYAVOLU SRINIVAS PAPA ,  CRENSHAW DARIUS LAMMONT ,  GRUNOW STEPHAN ,  BRENNAN KENNETH D ,  JOSHI SOMIT ,  LEAVY MONTRAY ,  MATZ PHILLIP D ,  AJMERA SAMEER KUMAR ,  SOLOMENTSEV YURI E

IPC: H01L21/8242

CPC classification number: H01L21/76834 ,  H01L21/288 ,  H01L21/76816 ,  H01L21/76849 ,  H01L23/5223 ,  H01L28/20 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The formation of a MIM (metal insulator metal) capacitor (164) and concurrent formation of a resistor (166) is disclosed. A copper diffusion barrier is formed over a copper deposition (110) that serves as a bottom electrode (170) of the capacitor (164). The copper diffusion barrier mitigates unwanted diffusion of copper from the copper deposition (110), and is formed via electro-less deposition such that little to none of the barrier material is deposited at locations other than over a top surface of the deposition of copper/bottom electrode. Subsequently, layers of dielectric (150) and conductive (152) materials are applied to form a dielectric (172) and top electrode (174) of the MIM capacitor (164), respectively, where the layer of conductive top electrode material (152) also functions to concurrently develop the resistor (166) on the same chip as the capacitor (164).

Abstract translation: 公开了形成MIM（金属绝缘体金属）电容器（164）和同时形成电阻器（166）。 铜扩散阻挡层形成在充当电容器（164）的底部电极（170）的铜沉积物（110）上。 铜扩散阻挡层减轻铜从铜沉积物（110）中不需要的扩散，并且通过无电沉积形成，使得阻挡材料很少或不是在除了铜/ 底部电极。 随后，分别施加电介质（150）和导电（152）材料层以形成MIM电容器（164）的电介质（172）和顶部电极（174），其中导电顶部电极材料层（152） 还用于在与电容器（164）相同的芯片上同时形成电阻器（166）。