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    HALBLEITERSPEICHEREINRICHTUNG SOWIE VERFAHREN ZU DEREN HERSTELLUNG
    1.
    发明申请
    HALBLEITERSPEICHEREINRICHTUNG SOWIE VERFAHREN ZU DEREN HERSTELLUNG 审中-公开
    半导体存储器装置及其制造方法

    公开(公告)号：WO2004049440A2

    公开(公告)日：2004-06-10

    申请号：PCT/DE2003/003885

    申请日：2003-11-24

    Applicant: INFINEON TECHNOLOGIES AG ,  KLOSE, Hyang-Sook ,  KLOSE, Jan, Aram ,  MIKOLAJICK, Thomas ,  WERNER, Wolfgang

    Inventor： MIKOLAJICK, Thomas ,  WERNER, Wolfgang

    IPC: H01L27/00

    CPC classification number: H01L45/1293 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1683

    Abstract: Es werden eine Halbleiterspeichereinrichtung (1) mit Phasenumwandlungsspeichereffekt sowie ein Verfahren zu deren Herstellung vorgeschlagen, bei welchem für ein Speicherelement (E) in einem Halbleitersubstrat (20) jeweils eine Hohlraumanordnung (H) mit mindestens einem Hohlraum (H1, H2) in räumlicher Nähe zum jeweiligen Speicherelement (E) derart vorgesehen wird, dass die thermische Kopplung des jeweiligen Speicherelements (E) zur Umgebung des Speicherelement (E) durch Reduktion der thermischen Leitfähigkeit zwischen Speicherelement (E) und der Umgebung vermindert ausgebildet wird.

    Abstract translation:

    有提出的半导体存储装置（1），相变存储器效应和它们的制备方法，式中，f导航用在半导体衬底（20）每一个都具有腔装置（H）R的存储元件（E）具有至少一个 在R＆AUML空腔（H1，H2）; umlicher N'AUML;他对每个存储元件（E）被设置成使得通过减小存储器元件之间的热传导BEAR能力各自的存储元件（E）到所述存储元件（E）的环境的热耦合（ E）和环境减少。

    SEMICONDUCTOR MEMORY CELL AND METHOD FOR PRODUCING SAID CELL
    6.
    发明申请
    SEMICONDUCTOR MEMORY CELL AND METHOD FOR PRODUCING SAID CELL 审中-公开
    半导体存储单元和方法及其

    公开(公告)号：WO2004077574A3

    公开(公告)日：2004-11-18

    申请号：PCT/DE2004000365

    申请日：2004-02-27

    Applicant: INFINEON TECHNOLOGIES AG ,  PINNOW CAY-UWE ,  MIKOLAJICK THOMAS

    Inventor： PINNOW CAY-UWE ,  MIKOLAJICK THOMAS

    IPC: H01L21/28 ,  H01L21/336 ,  H01L29/78

    CPC classification number: H01L29/6684 ,  H01L21/28291 ,  H01L29/78391

    Abstract: The invention relates to a semiconductor memory cell and a method for producing said cell. According to said method, the capacity (CFe) of a ferroelectric capacitor assembly, which is formed by the contact and/or a region of an essentially constant potential between the gate isolation region (GOX) and a ferroelectric region (16), the ferroelectric region (16) and an upper gate electrode (18), is configured in a reduced manner relative to conventional conditions and/or relative to the capacity (CGOX) of a gate insulation capacitor assembly, which is formed by the border surface between a channel region (K) and the gate insulation region (GOX), the gate insulation region (GOX) and the contact and/or the region of an essentially constant potential between the gate isolation region (GOX) and the ferroelectric region (16).

    Abstract translation: 已提出了用于制备半导体存储器单元和方法，其中该电容由所述接触和/或一个Gateisolatiosbereich（GOX）之间实质上恒定电位的区域上形成的强电介质电容器布置的（CFE）和Ferroelektrikumsbereich（16 ），（该Ferroelektrikumsbereich 16）和上栅电极（18），相对于传统的条件和/或容量（相对CGOX）的栅极绝缘电容器布置，这是一个沟道区之间形成（从界面K）和栅极绝缘区（GOX）， 栅极绝缘区（GOX）和所述接触和/或Gateisolatiosbereich（GOX）和Ferroelektrikumsbereich（16）之间的大致恒定的电势的区域形成或减少。

    METHOD FOR PRODUCING FERROELECTRIC CAPACITORS AND INTEGRATED SEMICONDUCTOR MEMORY CHIPS
    8.
    发明申请
    METHOD FOR PRODUCING FERROELECTRIC CAPACITORS AND INTEGRATED SEMICONDUCTOR MEMORY CHIPS 审中-公开
    用于生产FERRO电气电容和集成半导体内存块

    公开(公告)号：WO02065518A3

    公开(公告)日：2002-11-21

    申请号：PCT/DE0104790

    申请日：2001-12-18

    Applicant: INFINEON TECHNOLOGIES AG ,  KASKO IGOR ,  KROENKE MATTHIAS ,  MIKOLAJICK THOMAS

    Inventor： KASKO IGOR ,  KROENKE MATTHIAS ,  MIKOLAJICK THOMAS

    IPC: H01L27/105 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8246 ,  H01L27/115

    CPC classification number: H01L21/7687 ,  H01L21/76888 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/75

    Abstract: The invention relates to a method for the production of ferroelectric capacitors structured according to the stack principle, which are used in integrated semiconductor memory chips, wherein the individual capacitor modules (10, 11) have an oxygen barrier (4a, 4b) between a lower capacitor electrode (5a, 5b) and an electrically conductive plug (1a, 1b). At a site where it is not covered by the corresponding oxygen barrier (4a, 4b), an unstructured adhesive layer (3) is oxidized by the oxygen arising during the tempering process of the ferroelectric (6a, 6b) and forms insulating segments at said site in such a way that the lower capacitor electrodes (5a, 5b) of the ferroelectric capacitors (10, 11) are electrically insulated from one another. This makes it possible to eliminate the structuring step of the adhesive layer (3). Furthermore, said layer (3) serves as a getter of oxygen and inhibits the diffusion of oxygen to the plug.

    Abstract translation: 在用于生产在堆栈原则强电介质电容器建成为在集成的半导体存储器装置中使用的方法，所述个别电容器模块（10，11）具有氧阻隔（4A，4B）的下电容器电极之间（5A，5B）和导电插头（1A， 图1b）。 非结构化Hafschicht（3），在那里它们（4A，4B）是通过在铁电体的退火过程中的氧所覆盖的相应的氧屏障的不（6A，6B）形成，氧化的和形式的绝缘部分，使得下 电容器电极（图5a中，铁电电容器（10的​​5B9，11）彼此电绝缘。这消除了对粘接剂层（3），并且还，该层（3）可以被用于堵塞用于吸杂氧和抑制氧气扩散的图案化步骤。

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