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    DIGITAL SIGNAL CONTROLLER SECURE MEMORY PARTITIONING
    1.
    发明申请
    DIGITAL SIGNAL CONTROLLER SECURE MEMORY PARTITIONING 审中-公开
    数字信号控制器安全存储器分区

    公开(公告)号：WO2005116842A1

    公开(公告)日：2005-12-08

    申请号：PCT/US2005/017017

    申请日：2005-05-16

    Applicant: MICROCHIP TECHNOLOGY INCORPORATED ,  BOLES, Brian ,  MITRA, Sumit ,  MARSH, Steven

    Inventor： BOLES, Brian ,  MITRA, Sumit ,  MARSH, Steven

    IPC: G06F12/14

    CPC classification number: G06F12/1491

    Abstract: A controller offers various security modes for protecting program code and data stored in memory and ensuring that the protection is effective during all normal operating conditions of the controller. The controller includes configuration settings that segment program memory into a boot segment, a secure segment and a general segment, each with a particular level of security including no enhanced protection. The boot code segment (BS) is the most secure and may be used to store a secure boot loader. The secure code segment (SS) is useful for storing proprietary algorithms from third parties, such as algorithms for separating ambient noise from speech in speech recognition applications. The general code segment (GS) has the least security. The controller is configured to prevent program flow changes that would result in program code stored in high security segments from being accessed by program code stored in lower security segments. In addition, the processor may be configured to have associated secure data portions of both program memory, such as flash memory, and random access memory (RAM) corresponding to the BS, SS and GS. Attempts 15 to read data from or write data to the program memory or RAM associated with a higher security level from a lower security level are prevented from occurring.

    Abstract translation: 控制器提供各种安全模式，用于保护存储在存储器中的程序代码和数据，并确保在控制器的所有正常操作条件下保护有效。 控制器包括将程序存储器分割为引导段，安全段和通用段的配置设置，每个段具有特定级别的安全性，不包括增强的保护。 启动代码段（BS）是最安全的，可用于存储安全引导加载程序。 安全代码段（SS）用于存储来自第三方的专有算法，例如用于在语音识别应用中分离环境噪声与语音的算法。 一般代码段（GS）的安全性最低。 控制器被配置为防止程序流程改变，导致存储在高安全段中的程序代码被存储在较低安全段中的程序代码访问。 此外，处理器可以被配置为具有诸如闪存之类的程序存储器和对应于BS，SS和GS的随机存取存储器（RAM）的相关联的安全数据部分。 防止从较低安全级别读取数据或将数据写入与较高安全级别相关联的程序存储器或RAM的尝试。

    ANALOG-TO-DIGITAL CONVERTER WITH INTERCHANGE OF RESOLUTION AGAINST NUMBER OF SAMPLE AND HOLD CHANNELS
    4.
    发明申请
    ANALOG-TO-DIGITAL CONVERTER WITH INTERCHANGE OF RESOLUTION AGAINST NUMBER OF SAMPLE AND HOLD CHANNELS 审中-公开
    具有与样品和保持通道数量相关的分辨率的模数转数转换器

    公开(公告)号：WO2006091711A1

    公开(公告)日：2006-08-31

    申请号：PCT/US2006/006365

    申请日：2006-02-21

    Applicant: MICROCHIP TECHNOLOGY INCORPORATED ,  MITRA, Sumit, K. ,  HU, Harry ,  SCHIEKE, Pieter

    Inventor： MITRA, Sumit, K. ,  HU, Harry ,  SCHIEKE, Pieter

    IPC: H03M1/46 ,  H03M1/68 ,  H03M1/80

    CPC classification number: H03M1/004 ,  H03M1/007 ,  H03M1/1225 ,  H03M1/468 ,  H03M1/68 ,  H03M1/804

    Abstract: A successive approximation register analog-to-digital converter (SAR ADC) having a sample, hold and convert amplifier circuit may be configured for either a single channel SAR ADC or a multiple channel SAR ADC. Switches or metal connection options, e.g., bit configurable or metal mask configurable, respectively, may be used to configure a common capacitor area, a portion of which may be used as a reconfigurable charge-redistribution digital-to-analog converter (CDAC) of the SAR ADC as either a single channel sample, hold and convert 12-bit capacitor configuration or a four channel sample, hold and convert 10-bit capacitor configuration. All other parts of the SAR ADC circuitry may be substantially the same for either configuration, e.g., the resistive digital-to-analog converter (RDAC), successive approximation register (SAR), ADC controller, sample, hold and convert switches, comparator, etc, may be substantially the same for either the single or multiple channel SAR ADC configurations.

    Abstract translation: 具有采样，保持和转换放大器电路的逐次逼近寄存器模数转换器（SAR ADC）可以配置为单通道SAR ADC或多通道SAR ADC。 可以分别使用开关或金属连接选项，例如位配置或金属掩模可配置，以配置公共电容器区域，其一部分可用作可重新配置的电荷再分配数模转换器（CDAC） SAR ADC作为单通道采样，保持和转换12位电容配置或四通道采样，保持和转换10位电容配置。 SAR ADC电路的所有其他部分对于任一配置可能基本相同，例如电阻数模转换器（RDAC），逐次逼近寄存器（SAR），ADC控制器，采样，保持和转换开关，比较器， 对于单通道或多通道SAR ADC配置可能基本相同。

    FUNCTIONAL PATHWAY CONFIGURATION AT A SYSTEM/IC INTERFACE
    5.
    发明申请
    FUNCTIONAL PATHWAY CONFIGURATION AT A SYSTEM/IC INTERFACE 审中-公开
    功能路径配置在系统/ IC接口

    公开(公告)号：WO2004095364A2

    公开(公告)日：2004-11-04

    申请号：PCT/US2004/012134

    申请日：2004-04-20

    Applicant: MICROCHIP TECHNOLOGY INCORPORATED ,  BOLES, Brian ,  FISCHER, Richard ,  MITRA, Sumit ,  DRAKE, Rodney ,  BOWLING, Steven, A. ,  KRIS, Bryan ,  MARSH, Steven ,  HARB, Hassan

    Inventor： BOLES, Brian ,  FISCHER, Richard ,  MITRA, Sumit ,  DRAKE, Rodney ,  BOWLING, Steven, A. ,  KRIS, Bryan ,  MARSH, Steven ,  HARB, Hassan

    IPC: G06K19/00

    CPC classification number: G06F17/5068 ,  G06F15/76

    Abstract: The present invention relates generally to functional pathway configurations at the interfaces between integrated circuits (ICs) and the circuit assemblies with which the ICs communicate. More particularly, the present invention relates generally to the functional pathway configuration at the interface between one or more semiconductor integrated circuit dice, including an IC package and the circuitry of a system wherein the integrated circuit dice is a digital signal controller. Even more particularly, the present invention relates to a 18, 28, 40, 44, 64 or 80 pin functional pathway configuration for the interface between the digital signal controller and the system in which it is embedded.

    Abstract translation: 本发明一般涉及集成电路（IC）与IC连接的电路组件之间的接口上的功能通路配置。 更具体地说，本发明一般涉及包括IC封装的一个或多个半导体集成电路管芯与系统的电路之间的界面处的功能通路配置，其中集成电路管芯是数字信号控制器。 更具体地说，本发明涉及用于数字信号控制器和嵌入其中的系统之间的接口的18,28,40,44,64或80引脚功能通路配置。

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