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1.发明专利可變印章式印鑑及印鑑核對系統 VARIABLE IMPRINT SEAL AND SEAL VERIFICATION SYSTEM 失效可变印章式印鉴及印鉴核对系统 VARIABLE IMPRINT SEAL AND SEAL VERIFICATION SYSTEM
公开(公告)号：TW200634668A
公开(公告)日：2006-10-01
申请号：TW094141154
申请日：2005-11-23
Applicant: 野田將弘 NODA, MASAHIRO
Inventor： 野田將弘 NODA, MASAHIRO
IPC: G06T
Abstract: 〔課題〕提供有能有效防止印章偽造之可變印章式印鑑。〔解決手段〕具備有：保持原始印章的圖像資料之原始印章記憶部21、保持蓋印者的指紋資訊之指紋資訊記憶部22、讀取蓋印者指紋資訊之指紋讀取部23、核對指紋讀取部23讀取的指紋和指紋資訊記憶部22保持的指紋資訊，確認是否是合法蓋印者的認證之蓋印者認證部24、當蓋印者認證部24判定是合法蓋印者時，將原始印章記憶部21保持的原始印章圖像資料按特定的規則性進行變化的印章變形部25、輸出加上變化的印章圖像資料的蓋印部28。
Abstract in simplified Chinese: 〔课题〕提供有能有效防止印章伪造之可变印章式印鉴。〔解决手段〕具备有：保持原始印章的图像数据之原始印章记忆部21、保持盖印者的指纹信息之指纹信息记忆部22、读取盖印者指纹信息之指纹读取部23、核对指纹读取部23读取的指纹和指纹信息记忆部22保持的指纹信息，确认是否是合法盖印者的认证之盖印者认证部24、当盖印者认证部24判定是合法盖印者时，将原始印章记忆部21保持的原始印章图像数据按特定的守则性进行变化的印章变形部25、输出加上变化的印章图像数据的盖印部28。
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公开(公告)号：TWI402769B
公开(公告)日：2013-07-21
申请号：TW094141154
申请日：2005-11-23
Applicant: 野田將弘 , NODA, MASAHIRO
Inventor： 野田將弘 , NODA, MASAHIRO
IPC: G06T7/00
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公开(公告)号：WO2012047780A3
公开(公告)日：2012-06-14
申请号：PCT/US2011054545
申请日：2011-10-03
Applicant: IBM , ANDO TAKASHI , CHARNS LESLIE , CUMMINGS JASON , HUPKA JUKASZ J , KOLI DINESH R , KONNO TOMOHISA , KRISHNAN MAHADEVAIYER , LOFARO MICHAEL F , NALASKOWSKI JAKUB , NODA MASAHIRO , PENIGALAPATI DINESH K , YAMANAKA TATSUYA
Inventor： ANDO TAKASHI , CHARNS LESLIE , CUMMINGS JASON , HUPKA JUKASZ J , KOLI DINESH R , KONNO TOMOHISA , KRISHNAN MAHADEVAIYER , LOFARO MICHAEL F , NALASKOWSKI JAKUB , NODA MASAHIRO , PENIGALAPATI DINESH K , YAMANAKA TATSUYA
IPC: H01L21/336 , H01L21/304 , H01L29/78
CPC classification number: H01L21/31053 , H01L29/517 , H01L29/6653 , H01L29/66545
Abstract: Methods for polishing multiple dielectric layers to form replacement metal gate structures include a first chemical mechanical polish step to remove overburden and planarize a top layer to leave a planarized thickness over a gate structure. A second chemical mechanical polish step includes removal of the thickness to expose an underlying covered surface of a dielectric of the gate structure with a slurry configured to polish the top layer and the underlying covered surface substantially equally to accomplish a planar topography. A third chemical mechanical polish step is employed to remove the dielectric of the gate structure and expose a gate conductor.
Abstract translation: 用于抛光多个电介质层以形成替换金属栅极结构的方法包括第一化学机械抛光步骤，以去除覆盖层并平坦化顶层以在栅极结构上留下平坦化的厚度。 第二化学机械抛光步骤包括去除厚度以暴露栅极结构的电介质的下面覆盖的表面，其中浆料被配置成基本上等同地抛光顶层和下面的被覆表面以实现平面形貌。 采用第三种化学机械抛光步骤来去除栅极结构的电介质并露出栅极导体。
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4.发明申请CHEMICAL MECHANICAL PLANARIZATION PROCESSES FOR FABRICATION OF FINFET DEVICES 审中-公开用于制造FINFET器件的化学机械平面化方法
公开(公告)号：WO2012047770A3
公开(公告)日：2012-06-21
申请号：PCT/US2011054521
申请日：2011-10-03
Applicant: IBM , CHANG JOSEPHINE B , CHARNS LESLIE , CUMMINGS JASON E , GUILLORN MICHAEL A , HUPKA LUKASZ J , KOLI DINESH , KONNO TOMOHISA , KRISHNAN MAHADEVAIYER , LOFARO MICHAEL F , NALASKOWSKI JAKUB W , NODA MASAHIRO , PENIGALAPATI DINESH K , YAMANAKA TATSUYA
Inventor： CHANG JOSEPHINE B , CHARNS LESLIE , CUMMINGS JASON E , GUILLORN MICHAEL A , HUPKA LUKASZ J , KOLI DINESH , KONNO TOMOHISA , KRISHNAN MAHADEVAIYER , LOFARO MICHAEL F , NALASKOWSKI JAKUB W , NODA MASAHIRO , PENIGALAPATI DINESH K , YAMANAKA TATSUYA
IPC: H01L21/304 , H01L21/336 , H01L29/78
CPC classification number: H01L21/31053 , H01L29/517 , H01L29/6653 , H01L29/66545
Abstract: A planarization method includes planarizing a semiconductor wafer in a first chemical mechanical polish step to remove overburden and planarize a top layer leaving a thickness of top layer material over underlying layers. The top layer material is planarized in a second chemical mechanical polish step to further remove the top layer and expose underlying layers of a second material and a third material such that a selectivity of the top layer material to the second material to the third material is between about 1:1:1 to about 2:1:1 to provide a planar topography.
Abstract translation: 平面化方法包括在第一化学机械抛光步骤中平坦化半导体晶片以去除覆盖层并平坦化顶层，从而在顶层之上留下厚度的顶层材料。 顶层材料在第二化学机械抛光步骤中被平坦化，以进一步去除顶层并暴露第二材料和第三材料的下层，使得顶层材料对第二材料对第三材料的选择性在 约1：1至约2：1：1，以提供平面形貌。
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公开(公告)号：WO2012047780A2
公开(公告)日：2012-04-12
申请号：PCT/US2011/054545
申请日：2011-10-03
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION , ANDO, Takashi , CHARNS, Leslie , CUMMINGS, Jason , HUPKA, Jukasz, J. , KOLI, Dinesh, R. , KONNO, Tomohisa , KRISHNAN, Mahadevaiyer , LOFARO, Michael, F. , NALASKOWSKI, Jakub , NODA, Masahiro , PENIGALAPATI, Dinesh, K. , YAMANAKA, Tatsuya
Inventor： ANDO, Takashi , CHARNS, Leslie , CUMMINGS, Jason , HUPKA, Jukasz, J. , KOLI, Dinesh, R. , KONNO, Tomohisa , KRISHNAN, Mahadevaiyer , LOFARO, Michael, F. , NALASKOWSKI, Jakub , NODA, Masahiro , PENIGALAPATI, Dinesh, K. , YAMANAKA, Tatsuya
IPC: H01L21/336 , H01L29/78 , H01L21/304
CPC classification number: H01L21/31053 , H01L29/517 , H01L29/6653 , H01L29/66545
Abstract: Methods for polishing multiple dielectric layers to form replacement metal gate structures include a first chemical mechanical polish step to remove overburden and planarize a top layer to leave a planarized thickness over a gate structure. A second chemical mechanical polish step includes removal of the thickness to expose an underlying covered surface of a dielectric of the gate structure with a slurry configured to polish the top layer and the underlying covered surface substantially equally to accomplish a planar topography. A third chemical mechanical polish step is employed to remove the dielectric of the gate structure and expose a gate conductor.
Abstract translation: 用于抛光多个介电层以形成替代金属栅极结构的方法包括第一化学机械抛光步骤，以去除覆盖层并平坦化顶层以在栅极结构上留下平坦化厚度。 第二化学机械抛光步骤包括去除厚度以暴露栅极结构的电介质的下面覆盖表面，所述抛光被配置为基本上相同地抛光顶层和下面的覆盖表面以实现平面形貌。 采用第三个化学机械抛光步骤来去除栅极结构的电介质并暴露出栅极导体。
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Patent Agency Ranking
公开(公告)号：WO2011155636A1
公开(公告)日：2011-12-15
申请号：PCT/JP2011/063747
申请日：2011-06-08
Applicant: HOYA CORPORATION , KUDO, Kazunori , NODA, Masahiro
Inventor： KUDO, Kazunori , NODA, Masahiro
CPC classification number: A61F2/1672 , A61F2/0095 , A61F2/148 , A61F2/1662 , A61F2/1664 , A61F2/1667 , A61F2/167 , A61F2/1678 , A61F2/1691 , A61F9/0008 , A61F9/0017 , A61F2002/1681 , A61F2002/16903
Abstract: An exemplary ocular implant insertion system includes a case and a preloaded ocular implant insertion apparatus. The apparatus includes first and second movable structures that move the ocular implant in a predetermined sequence. The respective configurations of the case and the ocular implant insertion apparatus are such that the ocular implant insertion apparatus is not removable from the case when the ocular implant insertion apparatus is in the pre-use state and is removable after the first movable structure has moved at least a portion of the optical implant.
Abstract translation: 示例性的眼部植入物插入系统包括壳体和预加载的眼部植入物插入装置。 该装置包括以预定顺序移动眼部植入物的第一和第二可移动结构。 外壳和眼植入物插入装置的各自结构使得眼睛植入物插入装置不能从眼睛植入物插入装置处于使用前状态的情况下移除，并且在第一可移动结构移动之后可移除 至少一部分光学植入物。
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公开(公告)号：WO2012102765A1
公开(公告)日：2012-08-02
申请号：PCT/US2011/053230
申请日：2011-09-26
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION , CHARNS, Leslie , CUMMINGS, Jason, E. , HUPKA, Lukasz, J. , KOLI, Dinesh, R. , KONNO, Tomohisa , KRISHNAN, Mahadevaiyer , LOFARO, Michael, F. , NALASKOWSKI, Jakub , NODA, Masahiro , PENIGALAPATI, Dinesh , YAMANAKA, Tatsuya
Inventor： CHARNS, Leslie , CUMMINGS, Jason, E. , HUPKA, Lukasz, J. , KOLI, Dinesh, R. , KONNO, Tomohisa , KRISHNAN, Mahadevaiyer , LOFARO, Michael, F. , NALASKOWSKI, Jakub , NODA, Masahiro , PENIGALAPATI, Dinesh , YAMANAKA, Tatsuya
IPC: H01L21/304 , H01L21/76
CPC classification number: H01L21/31053 , C09G1/02 , H01L21/76224
Abstract: A polishing method includes polishing, in a first polish, a wafer to remove overburden and planarize a top layer leaving a portion remaining on an underlying layer. A second polishing step includes two phases. In a first phase, the top layer is removed and the underlying layer is exposed, with a top layer to underlying layer selectivity of between about 1:1 to about 2:1 to provide a planar topography. In a second phase, residual portions of the top layer are removed from a top of the underlying layer to ensure complete exposure of an underlying layer surface.
Abstract translation: 抛光方法包括在第一抛光剂中抛光晶片以去除覆盖层并平坦化顶层，留下保留在下层上的部分。 第二抛光步骤包括两个阶段。 在第一阶段中，去除顶层并暴露下层，其顶层至基层选择性为约1:1至约2:1，以提供平面形貌。 在第二阶段中，顶层的残余部分从下层的顶部去除，以确保下层的表面完全曝光。
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8.发明申请CHEMICAL MECHANICAL PLANARIZATION PROCESSES FOR FABRICATION OF FINFET DEVICES 审中-公开化学机械平面化工艺制造鳍式场效应晶体管器件
公开(公告)号：WO2012047770A2
公开(公告)日：2012-04-12
申请号：PCT/US2011/054521
申请日：2011-10-03
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION , CHANG, Josephine, B. , CHARNS, Leslie , CUMMINGS, Jason, E. , GUILLORN, Michael, A. , HUPKA, Lukasz, J. , KOLI, Dinesh , KONNO, Tomohisa , KRISHNAN, Mahadevaiyer , LOFARO, Michael, F. , NALASKOWSKI, Jakub, W. , NODA, Masahiro , PENIGALAPATI, Dinesh, K. , YAMANAKA, Tatsuya
Inventor： CHANG, Josephine, B. , CHARNS, Leslie , CUMMINGS, Jason, E. , GUILLORN, Michael, A. , HUPKA, Lukasz, J. , KOLI, Dinesh , KONNO, Tomohisa , KRISHNAN, Mahadevaiyer , LOFARO, Michael, F. , NALASKOWSKI, Jakub, W. , NODA, Masahiro , PENIGALAPATI, Dinesh, K. , YAMANAKA, Tatsuya
IPC: H01L21/304 , H01L21/336 , H01L29/78
CPC classification number: H01L21/31053 , H01L29/517 , H01L29/6653 , H01L29/66545
Abstract: A planarization method includes planarizing a semiconductor wafer in a first chemical mechanical polish step to remove overburden and planarize a top layer leaving a thickness of top layer material over underlying layers. The top layer material is planarized in a second chemical mechanical polish step to further remove the top layer and expose underlying layers of a second material and a third material such that a selectivity of the top layer material to the second material to the third material is between about 1:1:1 to about 2:1:1 to provide a planar topography.
Abstract translation: 平坦化方法包括在第一化学机械抛光步骤中平坦化半导体晶片，以去除覆盖层并平坦化顶层，在底层上留下顶层材料的厚度。 顶层材料在第二化学机械抛光步骤中被平面化以进一步去除顶层并暴露第二材料和第三材料的下层，使得顶层材料对第二材料对第三材料的选择性介于 约1:1:1至约2:1:1以提供平面形貌。
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公开(公告)号：JPH0935611A
公开(公告)日：1997-02-07
申请号：JP23188795
申请日：1995-07-18
Applicant: NODA MASAHIRO
Inventor： NODA MASAHIRO
Abstract: PROBLEM TO BE SOLVED: To make a breaker tripped by vibration, by fitting a specific article to the tip of the breaker switch. SOLUTION: A weight D easy to fall due by vibration is fitted to the tip of a breaker switch G. For instance, a split pin A is passed into a hole of the tip of the switch G to connect the weight D via a string B and a hook C. The weight D is placed on a mount E in the vicinity of the switch G by a double-sided tape F, etc.
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公开(公告)号：JPS6224058B2
公开(公告)日：1987-05-26
申请号：JP12141884
申请日：1984-06-13
Applicant: NODA MASAHIRO
Inventor： NODA MASAHIRO
IPC: A23L21/25
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